PM6341E1XC Datasheet, PDF (117/272 Pages) PMC-Sierra, Inc – E1 FRAMER/TRANSCEIVER

DATA SHEET
PMC-910419
ISSUE 8
PM6341 E1XC
E1 FRAMER/TRANSCEIVER
Register 0FH: E1XC Phase Status Word (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
PSB[8]
Default
X
X
X
X
X
X
X
X
This register contains the most significant bit of the 9-bit phase status word.
The PSB[8] bit toggles when the bit and timeslot count (from the Phase Status
Word LSB register) exceeds time slot 31, bit 7 or goes below time slot 0, bit 0.
The contents of the Phase Status Word registers (address 0EH and 0FH) are
internally updated on each receive line data frame pulse; a write to either E1XC
register address 0EH or 0FH must be performed to freeze the contents before
this register and the Phase Status Word (MSB) register can be read. The correct
sequence for reading the contents of the Phase Status Word are:
1. write to register address 0EH or 0FH
2. read register address 0FH (read Phase Status Word MSB)
3. read register address 0EH (read Phase Status Word LSB)
This write-before-read is analogous to the latching of performance monitor
counter values in PMON, and is required to ensure that the phase status word
value remains valid during the µP read. It is important to read the MSB register
before the LSB register because, once the Phase Status Word (LSB) register has
been read, the phase status word counter is unfrozen and the contents may
change immediately.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 101