PM6341E1XC Datasheet, PDF (200/272 Pages) PMC-Sierra, Inc – E1 FRAMER/TRANSCEIVER

DATA SHEET
PMC-910419
ISSUE 8
PM6341 E1XC
E1 FRAMER/TRANSCEIVER
Register 5DH: RSLC Block Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R
SQ
X
Bit 1
R
SQI
X
Bit 0
R/W
SQE
0
SQ:
The SQ bit reflects the current state of the squelch alarm.
SQI:
The SQI bit is set to logic 1 when the squelch alarm is either asserted or
deasserted. The bit is cleared to logic 0 when the register is read.
SQE:
The SQE bit enables the generation of an interrupt when the squelch alarm
changes state. When SQE is set to logic 1, the squelch alarm event is
enabled to generate an interrupt on the microprocessor INTB pin.
When the E1XC is reset, the SQE bit is set to logic 0, disabling a squelch event
from generating an interrupt.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 184