PM4354 Datasheet, PDF (308/463 Pages) PMC-Sierra, Inc – Four Channel Combined E1/T1/J1 Transceiver/Framer

RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
Registers 0C1H, 1C1H, 2C1H, 3C1H: RDLC Interrupt Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
INTE
INTC[6]
INTC[5]
INTC[4]
INTC[3]
INTC[2]
INTC[1]
INTC[0]
Default
0
0
0
0
0
0
0
0
The contents of the Interrupt Control Register should only be changed when the EN bit in the
Configuration Register is logic 0. This prevents any erroneous interrupt generation.
INTC[6:0]:
These bits control the assertion of FIFO fill level set point interrupts. A value of 0 in INTC[6:0]
is interpreted as decimal 128.
INTE:
The Interrupt Enable bit (INTE) must be set to logic 1 to allow the internal interrupt status to
be propagated to the INTB output.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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