PM8611 Datasheet, PDF (284/292 Pages) PMC-Sierra, Inc – SBSLITE™ Telecom Standard Product Data Sheet Preliminary

SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Table 31 Microprocessor Interface Write Access (Figure 40)
Symbol Parameter
Min
tS_AW
Address to Valid Write Set-up Time
5
tS_DW
Data to Valid Write Set-up Time
10
tS_ALW
Address to Latch Set-up Time
5
tH_ALW
Address to Latch Hold Time
5
tV_L
Valid Latch Pulse Width
2
tS_LW
Latch to Write Set-up
0
tH_LW
Latch to Write Hold
5
tH_DW
Data to Valid Write Hold Time
5
tH_AW
Address to Valid Write Hold Time
5
tV_WR
Valid Write Pulse Width
15
Figure 40 Microprocessor Interface Write Timing
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A[11:0]
ALE
(CSB+WRB)
D[7:0]
tSaw
tSalw
tVl
tSlw
tHaw
tHalw
tVwr
tHlw
tSdw
tHdw
VALID
Notes on Microprocessor Interface Write Timing
1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
2. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tS_ALW,
tH_ALW, tV_L, tS_LW, and tH_LW are not applicable.
3. Parameter tH_AW is not applicable if address latching is used.
4. When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 V point of the input to the 1.4 V point of the clock.
5. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds
from the 1.4 V point of the input to the 1.4 V point of the clock.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
283
Document ID: PMC-2010883, Issue 2