PM8611 Datasheet, PDF (238/292 Pages) PMC-Sierra, Inc – SBSLITE™ Telecom Standard Product Data Sheet Preliminary

SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
Register 0E8H: SYSDLL Configuration
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Reserved
Reserved
Unused
ERRORE
Reserved
LOCK
Default
X
X
X
X
X
X
X
X
X
X
0
0
X
X
0
0
The SYSDLL Configuration Register controls the basic operation of the DLL connected to the
SYSCLK input.
LOCK
The LOCK register is used to force the DLL to ignore phase offsets indicated by the phase
detector after phase lock has been achieved. When LOCK is set to logic zero, the DLL will
track phase offsets measured by the phase detector between the SYSCLK input and the DLL’s
reference clock. When LOCK is set to logic one, the DLL will not change the tap after the
phase detector indicates of zero phase offset between SYSCLK and the reference clock for
the first time.
ERRORE
The ERROR interrupt enable (ERRORE) bit enables the error indication interrupt. When
ERRORE is set high, an interrupt is generated upon assertion event of the ERR output and
ERROR register. When ERRORE is set low, changes in the ERROR and ERR status do not
generate an interrupt.
Reserved
These bits must be set to set low for correct operation of the SBSLITE.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
237
Document ID: PMC-2010883, Issue 2