PM7364 Datasheet, PDF (272/325 Pages) PMC-Sierra, Inc – Frame Engine and Datalink Manager

RELEASED
DATA SHEET
PMC-1960758
ISSUE 6
PM7364 FREEDM-32
FRAME ENGINE AND DATA LINK MANAGER
Register 0x0C : Cache Line Size/Latency Timer/Header Type
Bit
Bit 31
to
Bit 24
Bit 23
Bit 22
to
Bit 16
Bit 15
to
Bit 8
Bit 7
to
Bit 0
Type
R
R
R
R/W
R/W
Function
Reserved
Default
00H
MLTFNC
0
HDTYPE[6:0]
00H
LT[7:0]
00H
CLSIZE
00H
CLSIZE[7:0]:
The Cache Line Size (CLSIZE[7:0]) bits specify the size of the system
cacheline in units of dwords. The GPIC uses this value to determine the type
of read command to issue in a Master Read transfer. If the transfer size is
equal to one, the GPIC will issue a Memory Read command. If the transfer
size is equal to or less than the CLSIZE, the GPIC will issue a Memory Read
Line command. For transfers larger than CLSIZE, the GPIC issues a
Memory Read Multiple command.
LT[7:0]:
The Latency Timer (LT[7:0]) bits specify in units of the PCI clock, the value of
the Latency Timer for the GPIC. At reset the value is zero.
HDTYPE[6:0]:
The Header Type (HDTYPE[7:0]) bits specify the layout of the base address
registers. Only the 00H encoding is supported.
MLTFNC:
The Multi-Function (MLTFNC) bit specifies if the GPIC supports multiple PCI
functions. If this bit is set low, the device only supports one function and if the
bit is set high, the device supports multi-functions. The MLTFNC bit is set low
to indicate the GPIC only supports one PCI function.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 258