PM7364 Datasheet, PDF (189/325 Pages) PMC-Sierra, Inc – Frame Engine and Datalink Manager

RELEASED
DATA SHEET
PMC-1960758
ISSUE 6
PM7364 FREEDM-32
FRAME ENGINE AND DATA LINK MANAGER
Register 0x2C4 : RMAC Packet Descriptor Reference Ready Queue End
Bit
Bit 31
to
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Default
XXXXH
RPDRRQE[15]
0
RPDRRQE[14]
0
RPDRRQE[13]
0
RPDRRQE[12]
0
RPDRRQE[11]
0
RPDRRQE[10]
0
RPDRRQE[9]
0
RPDRRQE[8]
0
RPDRRQE[7]
0
RPDRRQE[6]
0
RPDRRQE[5]
0
RPDRRQE[4]
0
RPDRRQE[3]
0
RPDRRQE[2]
0
RPDRRQE[1]
0
RPDRRQE[0]
0
This register provides the Packet Descriptor Reference Ready Queue end
address.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 175