PM7324 Datasheet, PDF (246/473 Pages) PMC-Sierra, Inc – SATURN User Network Interface ATM Layer Solution

S/UNI-ATLAS
DATASHEET
PMC-1971154
ISSUE 7
PM7324 S/UNI-ATLAS
S/UNI-ATM LAYER SOLUTION
Register 0x183: Ingress VC Table External SRAM Row Select
Bit
Type
Function
Default
15
Unused
X
14
R/W
Row[14]
0
13
R/W
Row[13]
0
12
R/W
Row[12]
0
11
R/W
Row[11]
0
10
R/W
Row[10]
0
9
R/W
Row[9]
0
8
R/W
Row[8]
0
7
R/W
Row[7]
0
6
R/W
Row[6]
0
5
R/W
Row[5]
0
4
R/W
Row[4]
0
3
R/W
Row[3]
0
2
R/W
Row[2]
0
1
R/W
Row[1]
0
0
R/W
Row[0]
0
This register selects the rows which the microprocessor wants to access from the Ingress VC Table
for data in the VC Record indicated in register 0x181 and perform the operation specified by the RWB
bit. The contents of the VC Record Address register and this register should be written before
Register 0x182 is written.
ROW[14:0]:
ROW[14:0] indicate which of the 15 rows in the VC Record Table indicated by Register 0x181 is to be
written or read when a microprocessor access to the Ingress VC Table is to be done. If ROW[x] is set
to logic 1, row x of the Ingress VC Table will be written to or read from when Register 0x182 is written.
If ROW[14:0] are all set to logic 1, all 15 rows of the Ingress VC Table record address selected in
Register 0x181 will be written or read when a external SRAM access is triggered by writing to Register
0x182. The BUSY bit will be asserted until all the rows which are selected are written or read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE 238