PM7324 Datasheet, PDF (140/473 Pages) PMC-Sierra, Inc – SATURN User Network Interface ATM Layer Solution

S/UNI-ATLAS
DATASHEET
PMC-1971154
ISSUE 7
PM7324 S/UNI-ATLAS
S/UNI-ATM LAYER SOLUTION
8.24 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG
EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST are supported. The ATLAS identification code
is 073240CD hexadecimal.
8.25 Microprocessor Interface
The microprocessor interface is provided for device configuration, control and monitoring by an
external microprocessor. Normal mode registers, test mode registers, the external Ingress and
Egress VC Tables (external SRAM) and the internal PM and per-PHY policing RAM can be accessed
through this port. Test mode registers are used to enhance the testability of the ATLAS.
The interface has a 16-bit wide data bus. Multiplexed address and data operation is supported.
8.26 External SRAM Access
Microprocessor access to the external SRAM is provided to allow configuration of individual
connections. The Ingress Search Engine and Egress Cell Processor allocate a single cycle at the
beginning of each search/processing cycle for microprocessor accesses. The maximum time to
complete a external SRAM access is 1200 ns with a I/E SYSCLK frequency of 50 MHz. The average
completion time is less than 700ns. Upon placing the ISE in standby mode (default upon power up),
all SRAM cycles become available to the microprocessor. This allows for rapid configuration of the
device at startup. The Egress Cell Processor may also be placed in standby mode (default upon
power up) to allow all SRAM cycles for the microprocessor.
For externally requested write cycles, the ATLAS can cache all data rows for a single VC Table
connection in internal memory. The Ingress Search Engine maintains the data cache for externally
requested write cycles, and it can cache all rows of the Ingress VC Table. Similarly, the Egress Cell
Processor maintains the data cache for externally requested write cycles and it can cache all rows of
the Egress VC Table. The BUSYB signal is asserted when an Ingress or Egress external SRAM
access is pending. The signal is then deasserted when the external SRAM access is completed. The
IBUSY and EBUSY register status bits are also asserted until the external SRAM access is
completed.
For externally requested read cycles, the ATLAS may cache an entire VC Table worth of data in
internal memory. The Ingress Search Engine can be configured to read all rows of the Ingress VC
Table. Similarly, the Egress Cell Processor can be configured to read all rows of the Egress VC Table
for any connection. The BUSYB signal are asserted when an Ingress or Egress external access is
pending. The signals are then deasserted when the external SRAM access is completed. The IBUSY
and EBUSY register status bits are also asserted until the external SRAM access is completed. If the
ClearOnRead register bit is set, then a clearing write-back is made whenever a read of the Non-
Compliant Cell counts, CLP0 or CLP1 cell counts is made.
The BUSYB output can be connected to a DMA request input of a DMA controller. The rising edge of
BUSYB would initiate the next external SRAM access upon completion of the current access.
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