PM4341AT1XC Datasheet, PDF (214/288 Pages) PMC-Sierra, Inc – SINGLE DSX-1 TRANSCEIVER DEVICE

DATA SHEET
PMC-900602
ISSUE 7
PM4341A T1XC
T1 FRAMER/TRANSCEIVER
12 TIMING DIAGRAMS
Figure 13 - SLC®96 Transmit Datalink Interface
BTCLK
BTFP
TDLCLK
TDLSIG Sync Bit #4
Sync Bit #5
BTFP is the SLC®96 superframe pulse, occurring once every 9 ms. It indicates the
presence of the fourth Synchronization pattern bit on the TDLSIG input. The TDLSIG
pattern should be aligned to the BTFP superframe pulse as follows so that robbed
bit signalling can be inserted in the correct signalling frames:
BTFP
TDLCLK
TDLSIG
1 1 1 0 0 0 1 1 1 C1
S4 1 0 0 0 1 1
sync bits #4-12
sync bits #1-3
spoiler #2
The XBAS is configured to generate SLC®96 formatted data. The Data Link
Options register is programmed to provide access to the data link
(TXDMASIG=0). The Transmit Backplane Options is programmed for 1.544MHz
data rate, single-rail, with the frame alignment indication representing the
superframe alignment (BTXSFP=1). The dotted frame pulses are shown for
reference, indicating the subsequent frame boundaries of the superframe.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 196