PM6344-1 Datasheet, PDF (211/256 Pages) PMC-Sierra, Inc – QUADRUPLE E1 FRAMER

STANDARD PRODUCT
PMC-951013
ISSUE 5
PMC-Sierra, Inc.
Figure 24 - RFDL Normal Data and Abort Sequence
PM6344 EQUAD
QUADRUPLE E1 FRAMER
Serial Data
extracted from Flag D1 D2 D3
ESF FDL
RDLINT[x]
RDLEOM[x]
D[7:0]
D1 D2
B1 B2 B3
B1
Dn-1 Dn R C1 C2 Flag D1 R Abort
Dn-1
Dn-3 Dn-2
Dn B1 B2 B3
EOM
D1 B1
ABORT
EOM
This diagram shows the relationship between RFDL inputs and outputs for the
case where interrupts are programmed to occur when one byte is present in the
FIFO buffer. The RFDL is assumed to be operating in the interrupt driven mode.
Each read shown is composed of two register reads: first a read of the RFDL
Data Register, followed by a read of the RFDL Status Register. A read of the
RFDL Data Register sets the RDLINT[x] output to low if no more data exists in
the FIFO buffer. The status of the FE bit returned in the RFDL Status Register
read will indicate the FIFO buffer fill status as well. The RFDL Data Register read
Dn-2 is shown to occur after two bytes have been written into the buffer. The
RDLINT[x] output does not go low after the first RFDL Data Register read
because a data byte still remains to be read. The RDLINT[x] output goes low
after RFDL Data Register read Dn-1. The FE bit will be logic 0 in RFDL Status
Register read Dn-2 and logic 1 in RFDL Status Register read Dn-1.
The RDLEOM[x] output goes high as soon as the last byte in the frame is read
from the RFDL Data Register. The RDLINT[x] output will go low if the FIFO
buffer is empty. The next RFDL Status Register read will return a value of logic 1
for the EOM and FLG bits, and cause the RDLEOM[x] output of the RFDL to
return low.
In the next frame, the first data byte is received, and after a delay of ten bit
periods, it is written to the FIFO buffer, and read by the processor after the
interrupt. When the abort sequence is detected, the data received up to the
abort is written to the FIFO buffer and an interrupt generated. The processor
then reads the partial byte from the RFDL Data Register and the RDLEOM[x]
output is set high. The processor then reads the RFDL Status Register which will
return a value of logic 1 for the EOM and FLG bits, and set the RDLEOM[x]
198