PM6344-1 Datasheet, PDF (100/256 Pages) PMC-Sierra, Inc – QUADRUPLE E1 FRAMER

STANDARD PRODUCT
PMC-951013
ISSUE 5
PMC-Sierra, Inc.
PM6344 EQUAD
QUADRUPLE E1 FRAMER
Table 3
-
Previous PSB[7:6]
00
11
Current PSB[7:6]
11
00
Effect on PSB[8]
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The contents of the Phase Status Word registers (address 00EH and 00FH for
framer number 1) are internally updated on each receive line data frame pulse; a
write to either register address (00EH or 00FH for framer number 1) must be
performed to freeze the contents before this register and the Phase Status Word
(MSB) register can be read. The correct sequence for reading the contents of the
Phase Status Word of framer number 1 are:
1. Write to register address 00EH or 00FH
2. Read register address 00FH (read Phase Status Word MSB)
3. Read register address 00EH (read Phase Status Word LSB)
This write-before-read is analogous to the latching of performance monitor
counter values in PMON, and is required to ensure that the phase status word
value remains valid during the µP read. It is important to read the MSB register
before the LSB register because, once the Phase Status Word (LSB) register has
been read, the phase status word counter is unfrozen and the contents may
change immediately.
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