PM7384 Datasheet, PDF (167/358 Pages) PMC-Sierra, Inc – Frame Engine and Data Link Manager

DATA SHEET
PMC-1990445
ISSUE 5
PM7384 FREEDM-84P672
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x220 : RHDL Configuration
Bit
Bit 31
to
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
Function
Unused
Default
XXXXXXH
LENCHK
0
TSTD
0
Unused
X
Unused
X
Unused
X
Unused
X
Unused
X
Unused
X
Unused
X
Unused
X
This register configures all provisioned receive channels.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
TSTD:
The telecom standard bit (TSTD) controls the bit ordering of the HDLC data
transferred to the PCI host. When TSTD is set low, the least significant bit of
the each byte on the PCI bus (AD[0], AD[8], AD[16] and AD[24]) is the first
HDLC bit received and the most significant bit of each byte (AD[7], AD[15],
AD[23] and AD[31]) is the last HDLC bit received (datacom standard). When
TSTD is set high, AD[0], AD[8], AD[16] and AD[24] are the last HDLC bit
received and AD[7], AD[15], AD[23] and AD[31] are the first HDLC bit
received (telecom standard).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 156