PM7384 Datasheet, PDF (134/358 Pages) PMC-Sierra, Inc – Frame Engine and Data Link Manager

DATA SHEET
PMC-1990445
ISSUE 5
PM7384 FREEDM-84P672
FRAME ENGINE AND DATA LINK MANAGER 84P672
LENDIAN:
The Little Endian mode bit (LENDIAN) selects between Big Endian or Little
Endian format when reading packet data from and writing packet data to PCI
host memory. When LENDIAN is set low, Big Endian format is selected.
When LENDIAN is set high, Little Endian format is selected. Descriptor
references and the contents of descriptors are always transferred in Little
Endian Format. Please refer below for each format's byte ordering.
Table 21 – Big Endian Format
00 Bit 31
24
DWORD Address 04
BYTE 0
BYTE 4
•
•
•
n-4 BYTE n-4
23
16
BYTE 1
BYTE 5
•
•
•
BYTE n-3
15
87
Bit 0
BYTE 2
BYTE 3
BYTE 6
•
BYTE 7
•
•
•
•
•
BYTE n-2
BYTE n-1
Table 22 – Little Endian Format
00 Bit 31
24
DWORD Address 04
BYTE 3
BYTE 7
•
•
•
n-4 BYTE n-1
23
16
BYTE 2
BYTE 6
•
•
•
BYTE n-2
15
87
Bit 0
BYTE 1
BYTE 0
BYTE 5
•
BYTE 4
•
•
•
•
•
BYTE n-3
BYTE n-4
SOE_E:
The stop on error enable (SOE_E) bit determines the action the PCI
controller will take when a system or parity error occurs. When set high the
PCI controller will disconnect the PCI REQB signal from the PCI bus. This
prevents the GPIC from the becoming a master device on the PCI bus in
event of one of the following bits in the PCI Configuration Command/Status
register being set: DPR, RTABT, MABT and SERR. When the SOE_E bit is
set low the PCI controller will continue to allow master transactions on the
PCI bus. Setting this bit low after an error has occurred or clearing the
appropriate bit the PCI Configuration Command/Status register will reactivate
the PCI REQB signal and allow the GPIC to resume servicing the local
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 123