PL611-20 Datasheet, PDF (3/7 Pages) PhaseLink Corporation – Programmable Quick Turn Clock

PL611-20
Programmable Quick Turn Clock^TM
DIE SPECIFICATION
PAD LAYOUT AND DIE ID
Name
Size
Reverse side
Pad Opening
Die Thickness
Value
31.5x55.1 mil
GND
80 micron x 80 micron
10 mil
XIN 1
GND ²
GND 3
CLK0 ⁴
CLK1 5
9 ^XOUT
8 CLK2, OE, FSEL
7 VDD
6 VDD
PAD ASSIGNMENT and DESCRIPTION
Name
XIN
GND
Pad #
1
2
3
Die Pads
X (µm)
101.5
101.5
101.5
Y(µm)
1274.0
1075.0
878.4
Type
I
P
CLK0
4
101.5
671.8
O
CLK1
VDD
VDD
5
101.5
425.0
O
6
697
483.0
P
7
697
790.0
Note: CLK0=CLK1
Description
Crystal input.
GND connection.
Optional same frequency clock output (CLK0=CLK1). If the
clock output is not used, the pad should remain as ‘Do Not
Connect (DNC).
Programmable Clock Output.
VDD connection.
This programmable I/O pin can be configured as CLK2
(FIN or FIN/2) output, or OE input, or Frequency
Selection (FSEL) input pin. This pin has an internal
60KΩ pull up resistor.
CLK2, OE, FSEL
8
697
1024.0
O
State
0
1 (default)
OE
Tristate
CLK[0:1]
Normal
mode
FSEL
Select Freq. ‘1’
Select Freq. ‘2’
XOUT
9
697
1274.0
O Crystal output.
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Rev 07/06/05 Page 3