PL580-68 Datasheet, PDF (2/10 Pages) PhaseLink Corporation – 320-640MHz Low Phase Noise VCXO

(Preliminary) PL580-68/69
320-640MHz Low Phase Noise VCXO
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL580-68 (PECL)
PLL580-69 (LVDS)
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
PIN DESCRIPTIONS
Name
VDDANA
XIN
XOUT
DNC
OE_CTRL
VCON
GNDANA
LP
LM
GNDBUF
Q
VDDBUF
QBAR
GNDBUF
DNC
DNC
TSSOP
Pin number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3x3mm QFN
Pin number
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
Type
P
I
O
-
I
I
P
-
-
P
O
P
O
P
-
-
Description
VDD for analog Circuitry.
Crystal input pin. (See Crystal Specifications on page 4).
Crystal output pin. (See Crystal Specifications on page 4).
Do Not Connect
Output enable control pin. (See OE_CTRL Logic Levels above).
Voltage control input.
Ground for analog circuitry.
Tuning inductor connection. The inductor is recommended to be
a high Q small size 0402 or 0603 SMD component, and must be
placed between LP and adjacent LM pin. Place inductor as close
to the IC as possible to minimize parasitic effects and to
maintain inductor Q.
GND connection for output buffer circuitry.
PECL or LVDS output.
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
Complementary PECL, LVDS output.
GND connection for output buffer circuitry.
Do Not Connect
Do Not Connect
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 11/28/05 Page 2