PL560-XX Datasheet, PDF (2/15 Pages) PhaseLink Corporation – Analog Frequency Multiplier

Analog Frequency Multiplier
PL560-xx VCXO Family
VCON
L2X
X IN
XOUT
O scilla to r
A m p lifie r
O n ly re q u ire d in x4 d e s ig n s
F re q u e n cy
X2
F re q u e n cy
X4
L4X
Figure 2: Block Diagram of VCXO AFM
OE
QBAR
Q
Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 311.04 MHz, while Figure 4 shows the very
low rejection levels of sub-harmonics that correspond to the exceptionally low jitter performance.
Figure 3: Period Jitter Histogram at 311.04 MHz
Analog Frequency Multiplier (2x)
with 155.52MHz crystal
Figure 4: Spectrum Analysis at 311.04 MHz
Analog Frequency Multiplier (2x)
with sub-harmonics below –72 dBc
OE LOGIC SELECTION
OUTPUT
OESEL
OE
Output State
PECL
LVDS or CMOS
0 (Default)
1
0 (Default)
1
0 (Default)
1
0
1 (Default)
0
1 (Default)
0 (Default)
1
Enabled
Tri-state
Tri-state
Enabled
Tri-state
Enabled
Enabled
Tri-state
OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. Internally set to default through pull-down / -up.
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