PL660 Datasheet, PDF (12/15 Pages) PhaseLink Corporation – Analog Frequency Multiplier

Analog Frequency Multiplier
PL660 and PL663 XO Families
BOARD DESIGN AND LAYOUT CONSIDERATIONS
L2X and L4X: Reduce the PCB trace inductance to a
minimum by placing L2X and L4X as physically close to
their respective pins as possible. Also be sure to bypass
each VDD connection especially taking care to place a 0.01
uF bypass at the VDD side of L2X and L4X (see
recommended layout).
Crystal Connections: Be sure to keep the ground plane
under the crystal connections continuous so that the stray
capacitace is consistent on both crystal connections. Also
be sure to keep the crystal connections symmetrical with
respect to one another and the crystal connection pins of
the IC. If you chose to use a series capacitance and/or
inductor to fine tune the crystal frequency, be sure to put
symmetrical pads for this cap on both crystal pins (see
Cadj in recommended layout), even if one of the capacitors
will be a 0.01 uF and the other is used to tune the
frequency. To further maintain a symmetrical balance on a
crystal that may have more internal Cstray on one pin or
the other, place capacitor pads (Cbal) on each crystal lead
to ground (see recommended layout). R3rd is only
required if a 3^rd overtone crystal is used.
VDD and GND: Bypass VDDANA and VDDBUF with
separate bypass capacitors and if a VDD plane is used, feed
each bypass cap with its own via. Be sure to connect any
ground pin including the bypass caps with short via
connection to the ground plane.
OESEL: J1 is recommended so the same PCB layout can
be used for both OESEL settings.
PL660 (4x AFM) TSSOP Layout
PL663 (2x AFM) TSSOP Layout
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