PAS005B Datasheet, PDF (8/41 Pages) Pixart Imaging Inc. – SXGA Color/Mono Digital CMOS Image Sensor

PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
Reg_48[5]
CDS_pd
R/W
Reg_48[4]
ASP_pd
R/W
Reg_48[3]
path_chg
R/W
Reg_48[2]
even_path
R/W
Reg_48[1]
csbE
R/W
Reg_48[0]
csbO
R/W
Reg_49[5]
Test_EnH
R/W
Reg_49[4]
dqio_EnL
R/W
Reg_49[3]
scan_Dac
R/W
Reg_49[2]
scan_Color
R/W
Reg_49[1]
scan_Global
R/W
Reg_49[0]
pga_test_EnH
R/W
Reg_50[5]
sfswt_EnH
R/W
Reg_50[4]
offset_EnL
R/W
Reg_50[3]
zdly_plus
R/W
Reg_50[2]
cds_zero_EnH
R/W
Reg_50[1]
vga_ave_EnH
R/W
Reg_50[0]
cif_ave_EnH
R/W
Reg_51[7]
cds_fast_EnH
R/W
Reg_51[6]
dac_fast_EnH
R/W
Reg_51[5]
pga_fast_EnH
R/W
Reg_51[4]
adc_fast_EnH
R/W
Reg_51[3]
cds_EnL
R/W
Reg_51[2]
dac_EnL
R/W
Reg_51[1]
pga_EnL
R/W
Reg_51[0]
adc_EnL
R/W
Reg_52[5:4]
cdsbias[1:0]
R/W
Reg_52[3:2]
vlrst[1:0]
R/W
Reg_52[1:0]
vdday[1:0]
R/W
Reg_53[6]
reg_EnL
R/W
Reg_53[5:4]
regfast[1:0]
R/W
Reg_53[3:2]
vrefLG[1:0]
R/W
Reg_53[1:0]
vddd[1:0]
R/W
Reg_54[7]
T_gp1
R/W
Reg_54[6]
T_gp2
R/W
Reg_54[5]
extvdy_EnH
R/W
Reg_54[4]
vayNdrv_EnH
R/W
in redundancy rows
0 Analog CDS disable in redundancy rows
0 Analog signal path disable in redundancy rows
Combination of (single_path, path_chg):
00: even pixels processed by even signal path, odd
pixels processed by odd signal path
0 01: even pixels processed by odd signal path, odd
pixels processed by even signal path
10: all pixels are processed by the even signal path
11: all pixels are processed by the odd signal path
Useful only when mono mode and double path
readout, even pixels and odd pixels are all processed,
0 but just only either even or odd pixels are readout
0: for readout even path
1: for readout odd path
0 1 for closing the even analog signal path
0 1 for closing the odd analog signal path
0 Test enable high
0 dqio enable low
0 scan DAC(useful only when Test_EnH=1)
0 scan Color Gain(useful only when Test_EnH=1)
0 scan Global Gain(useful only when Test_EnH=1)
0 pga test enable high
0 Source follower dynamic switch enable high
0 Analog signal path offset enable low
0 Zeroing switch delay plus enable high
0 Zeroing switch in CDS enable high
0 VGA resolution averaged out enable high
0 CIF resolution averaged out enable high
0 CDS block fast enable high
0 DAC block fast enable high
0 PGA block fast enable high
0 ADC block fast enable high
0 CDS block enable low
0 DAC block enable low
0 PGA block enable low
0 ADC block enable low
0 CDS bias current option
0 VLRST voltage level option
0 VDDAY voltage level option
0 Regulator block enable low
1 Regulator current level option
0 Reference voltage (VRT-VRB) range option
0
Internal regulated digital power X_VDDD voltage
level option
0
0: CDS clock = even path clock
1: CDS clock = odd path clock
0
0: X_VDDD switch ON diode connect from VDDD
1: X_VDDD switch OFF diode connect from VDDD
0 External VDDAY enable high
0 VDDAY with NMOS drive enable high
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PixArt Imaging Inc.
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