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TDA8779H Datasheet, PDF (9/20 Pages) NXP Semiconductors – 10-bit converter interface ADC/DAC for quadrature transceiver
Philips Semiconductors
10-bit converter interface (ADC/DAC) for
quadrature transceiver
Product specification
TDA8779H
SYMBOL
PARAMETER
CONDITIONS
MIN.
STANDBY MODE OUTPUT DELAY TIMES; STDBYA; Tamb = 25 °C
td(stb)LH standby delay
−
(LOW-to-HIGH transition)
td(stb)HL start-up delay
−
(HIGH-to-LOW transition)
CROSSTALK ON THE ADC
αct
crosstalk on the ADC
fCLK(DAC) = 16.384 MHz; −50
fCLK(ADC) = 8.192 MHz;
Tamb = 25 °C; both DACs
switching between input
codes 0 and 1023; one
ADC 1 V (p-p) sine wave
at 4 MHz and the other
ADC set at the middle
code
DAC part
DIGITAL INPUTS: D0D TO D9D AND CLKD
VIL
LOW-level input voltage
Tamb = 25 °C
VIH
HIGH-level input voltage
Tamb = 25 °C
IIL
LOW-level input current
IIH
HIGH-level input current
DIGITAL INPUT; STDBYD
VIL
LOW-level input voltage
Tamb = 25 °C
VIH
HIGH-level input voltage
Tamb = 25 °C
IIL
LOW-level input current
IIH
HIGH-level input current
TIMING; Tamb = 25 °C (see Fig.5)
fCLK(max)
tCH
tCL
tr
tf
ts
th
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
clock rise time
clock fall time
input data set-up time
input data hold time
ANALOG OUTPUTS; note 3
0
2.0
−200
−10
0
2.0
−10
−10
20
20
20
−
−
11
0
Vo(p-p)
output voltage
full-scale
0.9
(peak-to-peak value)
ZoL
output load impedance
see Fig.6
−
−
TYP.
−
−
−55
−
−
−
−
−
−
−
−
−
−
−
4
4
−
−
1
15
0.3
MAX. UNIT
100
µs
100
µs
−
dB
0.8
VCCD2
0
+10
0.8
VCCD2
+10
+10
−
−
−
−
−
−
−
1.1
−
−
V
V
µA
µA
V
V
µA
µA
MHz
ns
ns
ns
ns
ns
ns
V
pF
kΩ
1999 Sep 16
9