TDA8779H Datasheet, PDF (8/20 Pages) NXP Semiconductors – 10-bit converter interface ADC/DAC for quadrature transceiver

Philips Semiconductors
10-bit converter interface (ADC/DAC) for
quadrature transceiver
Product specification
TDA8779H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
t_CL
clock pulse width LOW
t_r
clock rise time
t_f
clock fall time
ANALOG SIGNAL PROCESSING
20
−
−
4
−
4
−
ns
−
ns
−
ns
Linearity
INLA
integral non linearity
ramp input;
−
f_CLK = 20 MHz
DNLA
differential non linearity
full-scale; ramp input;
−
maximum missing codes
guaranteed: 20
f_CLK = 20 MHz
±2.25
±4
LSB
+1.55 to −0.9 +2.8 to −1.1 LSB
Noise floor; note 1
NF
noise floor
Harmonics; note 2
f_i = 4.43 MHz; 20 Msps −55
−71
−
dB
THD
total harmonic distortion
f_i = 4.43 MHz; 20 Msps −50
−58
−
dB
Spurious free dynamic range
SFDR spurious free dynamic
f_i = 4.43 MHz; 20 Msps 50
58
−
dB
range
Matching between the I and Q channels
∆V
amplitude matching
f_i = 4.43 MHz;
−
0.1
6
%
f_CLK = 20 MHz;
T_amb = 25 °C
∆ϕ
phase matching
f_i = 4.43 MHz;
−
0.05
2
deg
f_CLK = 20 MHz;
T_amb = 25 °C
Bandwidth
B
bandwidth (maximum
full-scale sine wave;
30
−
−
attenuation of −0.3 dB)
T_amb = 25 °C
50% full-scale sine wave; 30
−
−
T_amb = 25 °C
TIMING (THE OUTPUT DATA IS AVAILABLE AFTER THE MAXIMUM DELAY TIME t_d); C_L = 15 pF; T_amb = 25 °C (see Fig.3)
t_ds
sampling delay time
−
−
11
t_h
output hold time
5
−
−
t_d
output delay time
V_CCO = 3.3 V
−
12
−
V_CCO = 2.7 V
−
13
−
3-STATE OUTPUT DELAY TIMES; T_amb = 25 °C (see Fig.4)
t_dZH
output delay enable HIGH
−
10
−
t_dZL
output delay enable LOW
−
7.7
−
t_dHZ
output delay disable HIGH
−
15.5
−
t_dLZ
output delay disable LOW
−
14.9
−
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
1999 Sep 16
8