TDA8753A Datasheet, PDF (9/20 Pages) NXP Semiconductors – YUV 8-bit analog-to-digital interface

Philips Semiconductors
YUV 8-bit analog-to-digital interface
Product specification
TDA8753A
SYMBOL
PARAMETER
CONDITIONS
Timing (f_clk = 20 MHz; C_L = 15 pF); see Figs 7 and 10; note 7
f_clk
t_CP(H)
t_CP(L)
t_ds
t_hd
t_d
t_CLKr
t_CLKf
t_su;Href
t_hd;Href
t_r
t_f
t_CLP
maximum input clock frequency
clock pulse width HIGH
clock pulse width LOW
sampling delay
output hold time
output delay time
clock rise time
clock fall time
HREF set-up time
HREF hold time
data output rise time
data output fall time
minimum time for active clamp
pulse width
t_su;WE
t_hd;WE
t_XLXL
t_QVXH
WE set-up time
WE hold time
serial port clock cycle time
output data set-up to rising edge
of clock
f_xtal = 12 MHz
t_XHQH
output data hold time after rising
edge of clock
t_W
V50 pulse duration
t_VC
V50 to clock time
Sample rate converter (f_clk = 20 MHz)
ΦY
FUV
Y_fr
UV_fr
Y_step
UV_step
Y phase accuracy
UV phase accuracy
Y frequency response
UV frequency response
Y step size
UV step size
f_iY = 0 to 5 MHz
f_iUV = 0 to 1.5 MHz
f_iY = 0 to 5 MHz
f_iUV = 0 to 1.5 MHz
MIN.
20
22
22
−
7
−
3
3
7
3
−
−
2.3
7
3
1
700
50
2
2
−
−
−
−
−
−
TYP.
−
−
−
4
−
−
5
5
−
−
10
10
2.5
−
−
−
−
−
−
−
±1
±4
±0.5
±0.5
1
4
MAX.
−
−
−
−
−
32
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
ns
ns
ms
ms
ns
ns
dB
dB
ns
ns
1996 Jan 12
9