TDA8753A Datasheet, PDF (10/20 Pages) NXP Semiconductors – YUV 8-bit analog-to-digital interface

Philips Semiconductors
YUV 8-bit analog-to-digital interface
Product specification
TDA8753A
Notes to the Characteristics
1. V_DDA and V_DDD should be supplied from the same power supply and decoupled separately.
2. Measurement carried out using video amplifier type VM700A, where the video analog signal (Y channel) is
reconstructed via the DAC.
3. The input conditions are related as follows:
Y − V_i(p-p) = 1.26 V, f_i = 4.43 MHz
U and V − V_i(p-p) = 1.26 V, f_i = 1.5 MHz.
4. Supply voltage ripple rejection: SVR; relative variation of the full-scale range of analog input for a supply voltage
variation of 0.5 V. SVR = [∆ (V_I(0) − V_I(255)]/[V_I(o) − V_I(255)]/∆V_DDA.
5. The −1 dB bandwidth is the frequency value for which the analog reconstructed (glitch-free) output signal is
compressed in term of number of codes, by −1 dB (respectively for −3 dB bandwidth).
6. The signal-to-noise ratio without harmonics is measured under a 16 MHz clock frequency. This value is given for a
4.43 MHz input frequency on the Y channel (1.5 MHz on the U and V channels).
7. Output data acquisition: Output data is available after the maximum delay of t_d.
Table 2 Mode selection
MODE1
0
MODE0
0
MODE
normal configuration
Table 3 Output data coding
OUTPUT PORT
BIT
OUTPUT DATA
Y
Y7
Y₀7
Y₁7
Y₂7
Y₃7
Y6
Y₀6
Y₁6
Y₂6
Y₃6
Y5
Y₀5
Y₁5
Y₂5
Y₃5
Y4
Y₀4
Y₁4
Y₂4
Y₃4
Y3
Y₀3
Y₁3
Y₂3
Y₃3
Y2
Y₀2
Y₁2
Y₂2
Y₃2
Y1
Y₀1
Y₁1
Y₂1
Y₃1
Y0
Y₀0
Y₁0
Y₂0
Y₃0
U
U1
U₀7
U₀5
U₀3
U₀1
U0
U₀6
U₀4
U₀2
U₀0
V
V1
V₀7
V₀5
V₀3
V₀1
V0
V₀6
V₀4
V₀2
V₀0
1996 Jan 12
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