TDA8753A Datasheet, PDF (8/20 Pages) NXP Semiconductors – YUV 8-bit analog-to-digital interface

Philips Semiconductors
YUV 8-bit analog-to-digital interface
Product specification
TDA8753A
SYMBOL
PARAMETER
CONDITIONS
MIN.
Clamp and references [I_ref, DEC_ref(L) and V_ref(H)]
A_CL
clamping accuracy
Y
−4
U and V
−1
C_clamp
serial clamp capacitor
10
Z_ADC
internal impedance between
−
pin 29 and V_SSA
V_ref(H)
converter reference HIGH, applied
−
to pin 29
V_DECref(L)
converter reference voltage LOW, V_ref(H) = 2.38 V
−
applied to pin 28
Y analog input (INY); V_ref(H) = 2.38 V, V_ref(L) = 0.39 V; see Table 4
V_i(p-p)
input voltage, full range
(peak-to-peak value)
ramp input
−
I_i
input current
C_I
input capacitance
clamp non-active −
−
U,V analog inputs (INU and INV); V_ref(H) = 2.38 V, V_ref(L) = 0.39 V; see Table 4
V_i(p-p)
I_i
C_I
input voltage (peak-to-peak value) ramp input
−
input current
clamp non-active −
input capacitance
−
Inputs isolation
α_act
crosstalk between INY, INU and
−
INV
Digital outputs (Y0 to Y7, U1, U0, V1 and V0); see Table 3
V_OL
LOW level output voltage
I_OL = 1.6 mA
0
V_OH
HIGH level output voltage
I_OH = 0.4 mA
2.4
Analog signal processing (f_CLK = 20 MHz)
G_diff
Φ_diff
f_all
SVR
B
differential gain
note 2
−
differential phase
note 2
−
harmonics (full scale) all
note 3; Y
−
components
U and V
−
supply voltage ripple rejection
note 4
−
bandwidth
−1 dB; note 5
−
Transfer function (f_clk = 16 MHz)
INL
DNL
SNR
integral non-linearity
differential non-linearity
signal-to-noise ratio without
harmonics
ramp input
−
ramp input; Y
−
ramp input; U and V −
note 6; Y
41
U and V
42
TYP.
−
−
22
420
2.38
0.39
1.26
5
−
1.26
5
−
−
−
−
1.5
1.0
−53
−55
2
6
±0.75
±0.5
±0.6
44.5
46
MAX.
+1
+1
−
−
−
−
−
100
15
−
100
15
−50
0.5
V_DDD
−
−
−
−
−
−
−
±0.75
±0.9
−
−
UNIT
LSB
LSB
nF
Ω
V
V
V
nA
pF
V
nA
pF
dB
V
V
%
deg
dB
dB
%/V
MHz
LSB
LSB
LSB
dB
dB
1996 Jan 12
8