TDA8540 Datasheet, PDF (9/20 Pages) NXP Semiconductors – 4 X 4 video switch matrix

Philips Semiconductors
4 × 4 video switch matrix
Product specification
TDA8540
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Sub-address S0, S1 and S2 (pins 5, 7 and 11)
V_IH
HIGH level input voltage
V_IL
LOW level input voltage
4
−
V_CC V
0
−
1
V
Notes
1. Only for pins 6 and 8 when clamp action is not selected for these pins.
2. On all the video input pins, when non-I²C-bus control mode is selected or when clamp action is selected on
pins 6 and 8 (by I²C-bus control).
3. Connected between V_CC and pin 4 or pin 15.
4. Connected between AGND and pin 4 or pin 15.
CHARACTERISTICS
V_CC = 8 V; T_amb = 25 °C; gain condition, clamp condition and OFF state are controlled by the I²C-bus;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Supply
I_CC
supply current
without load
OFF state
−
20 30 mA
−
12 −
mA
Video inputs: IN0 to IN3 when the clamp is active (see Figs 3 and 4)
I_LI
V_clamp
I_clamp
input leakage current
input clamping voltage
input clamping current
V_I = 3 V
I_I = 5 µA
V_I = 0 V
−
0.4 1
µA
−
2.2 −
V
1.2 −
−
mA
Video inputs: IN0 and IN2 when the clamp is not active (see Fig.3)
V_bias
R_I
DC input bias level
input resistance
I_I = 0
−
2.9 −
V
−
10 −
kΩ
Video outputs: OUT0 to OUT3 (see Fig.5)
Z_O
R_O
ISO
V_O
V_bias
G_v
G_diff
ϕ_diff
NL
α_ct
SVRR
output impedance
OFF state
100 −
−
kΩ
output resistance
−
5
−
Ω
isolation
OFF state; f = 5 MHz 60 −
−
dB
output top sync level; (Y or CVBS)
0.4 0.7 1
V
output mean value for chrominance
signals
G = 2; load = 150 Ω 1.5 1.9 2.2 V
G = 1; without load 1
1.3 1.6 V
voltage gain
G = 1; f = 1 MHz
−1 0
+1 dB
G = 2; f = 1 MHz
5
6
7
dB
differential gain
note 1
−
0.5 3
%
differential phase
note 1
−
0.6 −
deg
non linearity
note 2
−
0.5 2
%
crosstalk attenuation between channels note 3
60 70 −
dB
supply voltage rejection
note 4
36 55 −
dB
1995 Feb 06
9