TDA8540 Datasheet, PDF (7/20 Pages) NXP Semiconductors – 4 X 4 video switch matrix

Philips Semiconductors
4 × 4 video switch matrix
Product specification
TDA8540
OEN (SUB = 02H): selects, for each output, if the output is active or high impedance, see Table 8.
Table 8 OEN (SUB = 02H) determines which output is active or high impedance
7 MSB
6
5
4
3
2
X⁽¹⁾
X⁽¹⁾
X⁽¹⁾
X⁽¹⁾
EN3⁽²⁾
EN2⁽²⁾
Notes
1. X = don’t care.
2. For j = 0 to 3: if ENj = 0 (1), then OUT j is high impedance (active).
1
EN1⁽²⁾
0 LSB
EN0⁽²⁾
After a power-on reset:
• The outputs are set to a high impedance state; the outputs are connected to IN0; the gains are set at two and inputs
IN0 and IN1 are clamped.
• Programming of the device is necessary because the outputs are in high impedance state.
Non-I²C-bus control
If the S0, S1 and S2 pins are all connected to V_CC the device will enter the non-I²C-bus mode.
After a power-on reset:
• Gain is set at two for all outputs.
• All inputs are clamped.
• All outputs are active.
• The matrix position is given by the SDA and SCL voltage level.
Table 9 Non-I²C-bus control
OUTPUT
OUT3
OUT2
OUT1
OUT0
SCL AND SDA
00
01
10
11
IN3
IN2
IN1
IN0
IN2
IN3
IN0
IN1
IN1
IN0
IN3
IN2
IN0
IN1
IN2
IN3
SCL and SDA act as normal input pins:
SCL interchanges (OUT3 and OUT2) with (OUT1 and OUT0).
SDA interchanges OUT3 with OUT2 and OUT1 with OUT0.
Remark: For use with chrominance signals, the clamp action must be overruled by external bias.
1995 Feb 06
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