TDA4691 Datasheet, PDF (9/26 Pages) NXP Semiconductors – Sync Processor with Clock SPC

Philips Semiconductors
Sync Processor with Clock (SPC)
Preliminary specification
TDA4691
SYMBOL
PARAMETER
CONDITIONS
MIN.
∆f₀/∆V₁₆ VCO sensitivity
4% control range;
−
depending on current
at pin 18
Input of external oscillator (pin 15)
V₁₅
pin voltage AC
V₁₅
pin voltage DC
R_int
internal resistance
C_int
internal capacitance
see Fig.4(b)
1
dependent on V₁₉
−
see Fig.4(b)
−
see Fig.4(b)
−
13.5 MHz buffer (pin 13)
V₁₃
V₁₃
V₁₃
t_r
t_f
D₁₃
C_L
∆T₁₃
clock HIGH level output voltage
clock HIGH level output voltage
clock LOW level output voltage
rise time
fall time
mark-to-space ratio
load capacitance
jitter on clock output
(peak-to-peak value)
I₁₃ = −1 mA;
V₁₂ = 4.5 V
I₁₃ = 0 mA
I₁₃ = 2 mA;
V₁₂ = 5.5 V
see Fig.5
see Fig.5
V₁₃ = 1.5 V
normal time constant
T_2;
measured between
lines 25 and 305
2.7
2.7
0
−
−
45/55
−
−
H-output buffer (pin 11)
V₁₁
H HIGH level output voltage
V₁₁
H HIGH level output voltage
V₁₁
H LOW level output voltage
t_r
rise time
t_f
fall time
t₃
time relation pin 13 to 11
t₄
time relation pin 13 to 11
t₅
H-pulse width
C_L
load capacitance
I₁₁ = −1 mA;
2.7
V₁₂ = 4.5 V
I₁₁ = 0 mA
2.7
I₁₁ = 2 mA;
0
V₁₂ = 5.5 V
see Fig.6
−
see Fig.6
−
see Fig.6
−
see Fig.6
3
see Fig.6
3.0
see Fig.6
−
Start of H-pulse (pin 14)
I₁₄
t₆₁
t₆₂
t₆₃
t₆₄
V₁₄ (t ₆₁)
current pin 14
time delay pulse between pin 20 and 11
time delay pulse between pin 20 and 11
time delay pulse between pin 20 and 11
time delay pulse between pin 20 and 11
voltage pin 14 (proportional to V₁₉)
see Fig.6
see Fig.6
see Fig.6
see Fig.6
−
−1.1
−0.6
3.8
5.0
0
TYP. MAX. UNIT
360
−
kHz/V
−
3
V
5
−
V
7
−
kΩ
4
−
pF
−
V₁₂
V
−
V₁₂
V
−
0.8 V
20
−
ns
20
−
ns
−
55/45 %
−
40
pF
−
2
ns
−
V₁₂
V
−
V₁₂
V
−
0.8 V
25
−
ns
25
−
ns
25
55
ns
−
−
ns
3.6
4.2 µs
−
40
pF
−
±100 µA
−1.3 −1.5 µs
−0.8 −1.0 µs
4.0
4.2 µs
5.2
5.4 µs
−
1
V
September 1993
9