TDA4691 Datasheet, PDF (10/26 Pages) NXP Semiconductors – Sync Processor with Clock SPC

Philips Semiconductors
Sync Processor with Clock (SPC)
Preliminary specification
TDA4691
SYMBOL
PARAMETER
V₁₄ (t ₆₂)
V₁₄ (t ₆₃)
V₁₄ (t ₆₄)
voltage pin 14 (proportional to V₁₉)
voltage pin 14 (proportional to V₁₉)
voltage pin 14 (proportional to V₁₉)
V-output buffer (pin 10)
V₁₀
V HIGH level output voltage
V₁₀
V HIGH level output voltage
V₁₀
V LOW level output voltage
t_r
rise time
t_f
fall time
t₃
time relation pin 13 to 10
t₄
time relation pin 13 to 10
t₅
V-pulse width
t₆
time delay between pin 20 and pin 10
C_L
load capacitance
Reference (pin 18)
V_REF
R₁₈
∆f
reference voltage
control current defining resistor
control range VCO
I_18/1
current pin 18 (±4%)
∆f_a
adjustable control range
I_18/3
current pin 18 (±3%)
I_18/3
current pin 18 (±5%)
50/60 Hz output (pin 7; open collector; see Fig.8)
V₇
output voltage pin 7; 50 Hz
≥ 287.5 lines/field = LOW
V₇
output voltage pin 7; 60 Hz
≤ 287 lines/field = HIGH
I₇
output leakage current
Sandcastle output (pin 6)
V₆
burstkey pulse
V₆
H-blanking pulse
independent from V_supply
V₆
V-blanking pulse
independent from V_supply
V₆
voltage pin 6 LOW
t_w
pulse width burstkey; 50 Hz
t_w
pulse width burstkey; 60 Hz
t₂
time relation between pin 20 and
burstkey
CONDITIONS
I₁₀ = −1 mA;
V₁₂ = 4.5 V
I₁₀ = 0 mA
I₁₀ = 2 mA;
V₁₂ = 5.5 V
see Fig.6
see Fig.6
see Fig.6
see Fig.6
see Fig.7
see Fig.7
see Fig.7
I₇ = 1 mA
I₇ = 2 mA
see Fig.9
at 6.5 V; see Fig.9
at 6.5 V; see Fig.9
see Fig.9
September 1993
10
MIN.
2
3.5
5
TYP.
2.4
4
5.5
MAX. UNIT
2.8 V
4.5 V
6
V
2.7
−
V₁₂
V
2.7
−
0
−
V₁₂
V
0.8 V
−
25
−
ns
−
25
−
ns
−
25
55
ns
3
−
−
ns
280
320
350 µs
12
16
20
µs
−
−
40
pF
1.1
1.2
1.3 V
8
−
30
kΩ
−
±4
−
%
−
105
−
µA
±3
−
±5
%
−
80
−
µA
−
120
−
µA
0
−
0.3 V
0
0.3
0.8 V
2.7
−
V₁₉
V
−
−
50
µA
9.5
10
12
V
4.3
4.5
4.7 V
2.3
2.5
2.7 V
0
0.2
0.8 V
4.0
4.3
4.7 µs
3.3
3.8
4.1 µs
2.2
2.5
2.8 µs