SAA7382 Datasheet, PDF (9/60 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM ELM

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (ELM)
Preliminary specification
SAA7382
6.1.21 DMACK
This signal is used in the ATAPI and Oak compatibility
modes during DMA transfers. The host pulls this signal
LOW in response to a DMARQ request to indicate that it is
ready to transfer data.
If this signal is not being used then it must be pulled HIGH
for SAA7382 to operate correctly.
6.1.22 IORDY/WAIT/HFBLB
In the ATAPI mode this signal is negated to extend the
host transfer cycle of any host register access. It is used in
PIO transfers. When IORDY is not negated it is in a
high-impedance state.
In the Sanyo compatibility mode the function of this signal
depends on the SELRQ input. If SELRQ is HIGH then
WAIT is set LOW to extend the host transfer cycle. If
SELRQ is LOW then WAIT acts as the DRQ signal in a
DMA transfer.
In the Oak compatibility mode this signal is the Host First
Byte Latch signal. A rising edge on this signal is used to
latch the first byte in a pseudo 16-bit DMA read. HFBLB
can only be HIGH when pseudo 16-bit DMA transfer mode
is selected.
6.1.23 SCRST/STEN
In the ATAPI or Oak compatibility mode this signal is pulled
LOW to reset the sub-CPU in response to a reset
command from the host.
In the Sanyo compatibility mode this signal is pulled LOW
to signal to the host that status bytes are available for
transfer.
6.1.24 DMARQ/DTEN
In the ATAPI or Oak compatibility mode this signal is
asserted when the SAA7382 is ready to transfer data
between the host and itself. In ATAPI single word and Oak
DMA transfers this occurs at every word. In ATAPI
multi-word DMA transfers this occurs at the start of the
transfer.
In the Sanyo compatibility mode this signal is pulled LOW
to signal to the host that data bytes are available for
transfer.
6.1.25 IRQ/EOP/HFBC
In the ATAPI mode this active HIGH signal indicates a host
interrupt request. It is asserted when the sub-CPU writes
to the ITRG register and is negated when the host reads
the status register or writes to the command register.
In the Sanyo compatibility mode this signal is set LOW
when the last data byte is transferred to or from the host.
In the Oak compatibility mode this is the Host First Byte
Cycle output and is HIGH while the first byte in the pseudo
16-bit DMA transfer is accessed. It should be used to
inhibit non-DMA transactions while the first byte is latched.
6.1.26 HD0 TO HD15
These are the bidirectional Host Data signals. In the Sanyo
and Oak compatibility modes HD8 to HD15 are never
used.
6.1.27 DA0/CMD
In the ATAPI mode this is the host Data Address 0 signal.
In the Sanyo and Oak compatibility modes this input
selects between command or data transfers.
6.1.28 DA1
This is the ATAPI Data Address 1 signal.
6.1.29 DA2/ EJECT
In the ATAPI mode this is the Data Address 2 signal. In the
Oak compatibility mode this is the door switch input pin. Its
state is reflected in the TSTAT register.
6.1.30 CS2/SELRQ
In the ATAPI mode this is the Chip Select 2 signal. In the
Oak and Sanyo compatibility mode this is the data transfer
mode select input. It is used to select between PIO and
DMA transfers.
6.1.31 IOCS16
This open-collector signal is used in the ATAPI mode to
signal to the host that a 16-bit data port has been
addressed. It is not activated during DMA transfers.
1996 Apr 25
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