SAA7382 Datasheet, PDF (18/60 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM ELM

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (ELM)
Preliminary specification
SAA7382
7.7.14 STAT0
Resetting the chip clears all bits in this register.
Table 9 STAT0 register bits
BIT
NAME
FUNCTION
7
CRCOK Cyclic redundancy check not OK = 0; Cyclic redundancy check OK = 1. Set by the
EDC in accordance with the results of the CRC check.
6
ILSYNC Sync pattern detected at word count 0 to 1174 or 1176 onwards = 1. This bit is set to
logic 1 if the sync pattern in the incoming data is detected between word counts
0 and 1174 or 1176 to infinity, and the decoder has been retimed. Due to the
presence of the cache RAM, it is necessary to stop error correction also when long
blocks have been detected.
5
NOSYNC Sync pattern inserted by sync interpolator not coincident with data sync = 1. This bit
is set to logic 1, if the word counter reaches 1175 and no sync pattern has been
detected in the input data. It indicates that the sync interpolator circuit inserted a
sync.
4
LBLK
With SYIEN = 0, no sync found. Data block size has been extended = 1. This bit is
set to logic 1, if the sync interpolator was switched off, and if the sync interpolator
indicated that sync insertion was necessary. This condition causes the block length to
be extended.
3
Reserved
2
SBLK
Short block indication = 1. This bit is set to logic 1 if the decoder is not retimed when
a sync pattern is detected in an incorrect word location, and is ignored while the
SYDEN bit is set to logic 0.
1
ERABLK One or more bytes of the block are flagged with C2 flags = 1. This bit is set to logic 1
if one or more bytes of the current block contain erasures as indicated by the C2PO
input.
0
UCEBLK Uncorrectable errors in block = 1. This bit is set to logic 1 when one or more bytes of
the current block remain in error after the error correction process.
7.7.15 STAT1
Resetting the chip clears all bits in this register.
The bits in this register indicate the reliability of data in the HEAD0 to HEAD3 registers. Bits MINERR, SECERR,
BLKERR and MODERR indicate errors in the minutes, seconds, frames and mode bytes in the header of the current
block. Bits SH0ERR to SH3ERR indicate errors in the respective bytes in the sub-header.
Table 10 STAT1 register bits
BIT 7
BIT 6
MINERR SECERR
BIT 5
BLKERR
BIT 4
MODER
BIT 3
SH0ERR
BIT 2
SH1ERR
BIT 1
SH2ERR
BIT 0
SH3ERR
1996 Apr 25
18