SAA7382 Datasheet, PDF (25/60 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM ELM

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (ELM)
Preliminary specification
SAA7382
7.8 Sub-CPU interface
The sub-CPU interface is a 3-wire synchronous serial protocol. The interface uses three signals; SYN is used as a
synchronization signal, SDA is the bidirectional open-collector data signal and SCL is the bit clock.
The start of a command is signalled by a pulse on the SYN input. After this pulse an 8-bit address byte will be sent by
the sub-CPU. The format of this address byte is given in Table 24.
Table 24 Address byte format
BIT
NAME
DESCRIPTION
7
device If this bit is clear then the command will be for the SAA7382 otherwise the command is
select for another device and the SAA7382 will not respond.
6
address This bit controls the auto-increment function. After every byte has been read from or
mode written to the SAA7382 the address register is updated so that it is not necessary to
re-send the address to read or write the following byte. The way the address register is
updated is determined by the address mode bit. If the address mode bit is logic 0 then
the address register will increment by 1 if it is currently in the range 1 to 14 or 16 to 30. If
the address register is currently 15 or 31 then it will update to 0, if the address register is
at logic 0 then it will remain at address 0. If the address mode bit is logic 1 then the
address register will update in the following sequences;
Read: APCMD/COMIN -> APCMD/COMIN, IFSTAT -> DBCL -> DBCH -> HEAD0 ->
HEAD1 -> HEAD2 -> HEAD3 -> PTL -> PTH -> PTHH -> WAL -> WAH -> WAHH ->
STAT0 -> STAT1 -> STAT2 -> STAT3 -> APCMD/COMIN, ACMD -> ASMAT -> ADCTR
-> ADRSEL -> AINTR -> AFEAT -> APCMD/COMIN.
Write: ADATA/SBOUT -> ADATA/SBOUT, IFCTRL -> DBCL -> DBCH -> DACL ->
DACH -> DACHH -> DTRG -> DTACK -> WAL -> WAH -> WAHH -> CTRL0 -> CTRL1
-> PTL -> PTH -> PTHH -> SUB_L ->SUB_H -> 21 -> INCNF -> MEMS -> ASTAT ->
ITRG -> ADRADR -> ASAMT -> DTCTR -> ADRSEL -> AINTR -> AERR ->
ADATA/SBOUT.
5
register This is the address that is loaded into the address register and determines which register
4
number is accessed.
3
2
1
0
R/W If this bit is set to logic 0 then the sub-CPU will send one or more data bytes after the
address byte. This data will be loaded into the specified registers. If this bit is set to
logic 1 then after sending the address byte the sub-CPU will clock out the contents of
one or more registers.
1996 Apr 25
25