80C453 Datasheet, PDF(9/23 Page) NXP Semiconductors – CMOS single-chip 8-bit microcontrollers

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80C453 Datasheet, PDF (9/23 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontrollers

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Philips Semiconductors

CMOS single-chip 8-bit microcontrollers

Preliminary specification

80C453/83C453/87C453

SM0

SM1

SM2

REN

TB8

RB8

SCON

(98H)

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

COMPARATOR

IN UART MODE 2 OR MODE 3 AND SM2 = 1:

INTERRUPT IF REN=1, RB8=1 AND âRECEIVED ADDRESSâ = âPROGRAMMED ADDRESSâ

â WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES

â WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

Figure 7. UART Multiprocessor Communication, Automatic Address Recognition

SU00045

SPECIAL FUNCTION REGISTER ADDRESSES

Special function register addresses for the device are identical to

those of the 80C51, except for the additional registers listed in

Table 2.

Enhanced UART

The UART operates in all of the usual modes that are described in

the first section of this book for the 80C51. In addition the UART can

perform framing error detect by looking for missing stop bits, and

automatic address recognition. The 87C453 UART also fully

supports multiprocessor communication as does the standard

80C51 UART.

When used for framing error detect the UART looks for missing stop

bits in the communication. A missing bit will set the FE bit in the

SCON register. The FE bit shares the SCON.7 bit with SM0 and the

function of SCON.7 is determined by PCON.6 (SMOD0) (see

Figure 5). If SMOD0 is set then SCON.7 functions as FE. SCON.7

functions as SM0 when SMOD0 is cleared. When used as FE

SCON.7 can only be cleared by software. Refer to Figure 6.

Automatic Address Recognition

Automatic Address Recognition is a feature which allows the UART

to recognize certain addresses in the serial bit stream by using

hardware to make the comparisons. This feature saves a great deal

of software overhead by eliminating the need for the software to

examine every serial address which passes by the serial port. This

feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART

modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be

automatically set when the received byte contains either the âGivenâ

address or the âBroadcastâ address. The 9 bit mode requires that

the 9th information bit is a 1 to indicate that the received information

is an address and not data. Automatic address recognition is shown

in Figure 7.

The 8 bit mode is called Mode 1. In this mode the RI flag will be set

if SM2 is enabled and the information received has a valid stop bit

following the 8 address bits and the information is either a Given or

Broadcast address.

Mode 0 is the Shift Register mode and SM2 is ignored.

Using the Automatic Address Recognition feature allows a master to

selectively communicate with one or more slaves by invoking the

Given slave address or addresses. All of the slaves may be

contacted by using the Broadcast address. Two special Function

Registers are used to define the slaveâs address, SADDR, and the

address mask, SADEN. SADEN is used to define which bits in the

SADDR are to b used and which bits are âdonât careâ. The SADEN

mask can be logically ANDed with the SADDR to create the âGivenâ

address which the master will use for addressing each of the slaves.

Use of the Given address allows multiple slaves to be recognized

while excluding others. The following examples will help to show the

versatility of this scheme:

Slave 0

SADDR =

SADEN =

Given =

1100 0000

1111 1101

1100 00X0

Slave 1

SADDR =

SADEN =

Given =

1100 0000

1111 1110

1100 000X

In the above example SADDR is the same and the SADEN data is

used to differentiate between the two slaves. Slave 0 requires a 0 in

bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is

ignored. A unique address for Slave 0 would be 1100 0010 since

slave 1 requires a 0 in bit 1. A unique address for slave 1 would be

1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be

selected at the same time by an address which has bit 0 = 0 (for

slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed

with 1100 0000.

In a more complex system the following could be used to select

slaves 1 and 2 while excluding slave 0:

Slave 0

SADDR =

SADEN =

Given =

1100 0000

1111 1001

1100 0XX0

Slave 1

SADDR =

SADEN =

Given =

1110 0000

1111 1010

1110 0X0X

Slave 2

SADDR =

SADEN =

Given =

1110 0000

1111 1100

1110 00XX

1996 Aug 15

3-319

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