80C453 Datasheet, PDF (14/23 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontrollers

Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Preliminary specification
80C453/83C453/87C453
AC ELECTRICAL CHARACTERISTICS
T_amb = 0°C to +70°C or –40°C to +85°C, V_CC = 5V ±10%, V_SS = 0V
SYMBOL FIGURE
PARAMETER
1/t_CLCL
t_LHLL
9
t_AVLL
9
t_LLAX
9
t_LLIV
9
t_LLPL
9
t_PLPH
9
t_PLIV
9
t_PXIX
9
t_PXIZ
9
t_AVIV
9
t_PLAZ
9
Data Memory
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
t_RLRH
10, 11
t_WLWH
10, 11
t_RLDV
10, 11
t_RHDX
10, 11
t_RHDZ
10, 11
t_LLDV
10, 11
t_AVDV
10, 11
t_LLWL
10, 11
t_AVWL
10, 11
t_QVWX
10, 11
t_WHQX
10, 11
t_RLAZ
10, 11
t_WHLH
10, 11
Shift Register
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
RD low to address float
RD or WR high to ALE high
t_XLXL
12 Serial port clock cycle time
t_QVXH
12 Output data setup to clock rising edge
t_XHQX
12 Output data hold after clock rising edge
t_XHDX
12 Input data hold after clock rising edge
t_XHDV
12 Clock rising edge to input data valid
Port 6 input (input rise and fall times = 5ns)
t_FLFH
t_ILIH
t_DVIH
t_IHDZ
t_IVFV
15 PE width
15 IDS width
15 Data setup to IDS high or PE high
15 Data hold after IDS high or PE high
16 IDS to BFLAG (IBF) delay
16MHz CLOCK
MIN
MAX
85
22
32
150
32
142
82
0
37
207
10
VARIABLE CLOCK
MIN
MAX
3.5
16
2t_CLCL–40
t_CLCL–40
t_CLCL–30
t_CLCL–30
3t_CLCL–45
0
4t_CLCL–100
3t_CLCL–105
t_CLCL–25
5t_CLCL–105
10
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
275
6t_CLCL–100
ns
275
6t_CLCL–100
ns
147
5t_CLCL–165
ns
0
0
ns
65
2t_CLCL–60
ns
350
8t_CLCL–150
ns
397
9t_CLCL–165
ns
137
239
3t_CLCL–50
3t_CLCL+50
ns
122
4t_CLCL–130
ns
13
t_CLCL–50
ns
13
t_CLCL–50
ns
0
0
ns
23
103
t_CLCL–40
t_CLCL+40
ns
750
12t_CLCL
ns
492
10t_CLCL–133
ns
8
2t_CLCL–117
ns
0
0
ns
492
10t_CLCL–133
ns
209
3t_CLCL+20
ns
209
3t_CLCL+20
ns
0
0
ns
30
30
ns
130
130
ns
1996 Aug 15
3-324