74F842 Datasheet, PDF (9/12 Pages) NXP Semiconductors – Bus interface latches

Philips Semiconductors
10-bit bus interface latches, non-inverting/inverting
(3-State)
Product data
74F841/74F842
TEST CIRCUIT AND WAVEFORMS
V_CC
V_IN
PULSE
GENERATOR
V_OUT
R_L
D.U.T.
R_T
C_L R_L
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST
t_PLZ
t_PZL
All other
SWITCH
closed
closed
open
7.0 V
NEGATIVE
PULSE
90%
POSITIVE
PULSE
10%
t_w
V_M
10%
t_{THL (}t_f )
V_M
10%
t_{TLH (}t_r )
t_{TLH (}t_r )
90%
V_M
t_w
t_{THL (}t_f )
90%
V_M
Input Pulse Definition
90%
AMP (V)
0V
AMP (V)
10%
0V
DEFINITIONS:
R_L = Load resistor;
see AC electrical characteristics for value.
C_L = Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R_T = Termination resistance should be equal to Z_OUT of
pulse generators.
INPUT PULSE REQUIREMENTS
family
amplitude ^VM rep. rate
t_w
t_TLH
74F
3.0 V 1.5 V 1 MHz 500 ns 2.5 ns
t_THL
2.5 ns
SF00777
2004 Jan 23
9