74F842 Datasheet, PDF (7/12 Pages) NXP Semiconductors – Bus interface latches

Philips Semiconductors
10-bit bus interface latches, non-inverting/inverting
(3-State)
Product data
74F841/74F842
AC ELECTRICAL CHARACTERISTICS for 74F841/74F842
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T_amb = +25 °C
V_CC = +5.0 V
C_L = 50 pF; R_L = 500 Ω
MIN
TYP MAX
T_amb = 0 °C to +70 °C
V_CC = +5.0 V ± 10%
C_L = 50 pF; R_L = 500 Ω
MIN
MAX
t_PLH
Propagation delay
t_PHL
Dn to Qn
t_PLH
Propagation delay
t_PHL
LE to Qn
Waveform 1, 2
2.0
2.5
4.0
4.5
7.5
7.5
2.0
2.5
8.0
8.0
74F841
Waveform 1, 2
4.5
4.0
6.5
6.0
9.5
9.0
4.0
3.5
10.0
9.5
t_PLH
Propagation delay
t_PHL
Dn to Qn
t_PLH
Propagation delay
t_PHL
LE to Qn
Waveform 1, 2
3.5
3.0
5.5
5.0
8.5
8.0
4.5
4.0
9.0
8.5
74F842
Waveform 1, 2
5.0
4.5
7.0
10.0
6.5
9.0
3.0
3.0
10.5
9.5
t_PZH
Output enable time
Waveform 4
2.5
4.5
8.0
2.0
8.5
t_PZL
HIGH or LOW-level OE to Qn or Qn
Waveform 5
4.0
6.0
9.5
3.0
10.5
t_PHZ
Output disable time
Waveform 4
1.0
4.5
8.0
1.0
8.5
t_PLZ
HIGH or LOW-level OE to Qn or Qn
Waveform 5
1.0
5.0
8.0
1.0
8.5
UNIT
ns
ns
ns
ns
ns
ns
AC SET-UP REQUIREMENTS for 74F841/74F842
SYMBOL
PARAMETER
TEST
CONDITION
t_s(H)
t_s(L)
t_h(H)
t_h(L)
t_w(H)
t_h(H)
t_h(L)
t_w(H)
Set-up time, HIGH or LOW
Dn to LE
Hold time, HIGH or LOW
Dn to LE
LE pulse width, HIGH
Hold time, HIGH or LOW
Dn to LE
LE pulse width, HIGH
74F841
74F842
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
LIMITS
T_amb = +25 °C
V_CC = +5.0 V
C_L = 50 pF; R_L = 500 Ω
MIN
TYP
T_amb = 0 °C to +70 °C
V_CC = +5.0 V ± 10%
C_L = 50 pF; R_L = 500 Ω
MIN
MAX
0.0
–
1.0
–
0.0
–
1.0
–
2.5
–
3.0
–
3.0
–
4.0
–
3.5
–
4.0
–
3.0
–
3.5
–
3.5
–
4.5
–
3.0
–
3.0
–
UNIT
ns
ns
ns
ns
ns
2004 Jan 23
7