TDA8755 Datasheet, PDF (8/20 Pages) NXP Semiconductors – YUV 8-bit video low-power analog-to-digital interface

Philips Semiconductors
YUV 8-bit video low-power
analog-to-digital interface
Product specification
TDA8755
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Timing (f_clk = 20 MHz); note 6; see Figs 3 to 7
t_ds
sampling delay time
−
1
−
ns
t_h
output hold time
7
−
−
ns
t_d
output delay time
−
33
42
ns
t_dZH
3-state output delay time
enable-to-HIGH
−
10
14
ns
t_dZL
3-state output delay time
enable-to-LOW
−
10
14
ns
t_dHZ
3-state output delay time
disable-to-HIGH
−
8
11
ns
t_dLZ
3-state output delay time
disable-to-LOW
−
4
6
ns
t_r
clock rise time
3
5
−
ns
t_f
clock fall time
3
5
−
ns
t_su
HREF set-up time
7
−
−
ns
t_h
HREF hold time
3
−
−
ns
t_r
data output rise time
−
12
−
ns
t_f
data output fall time
−
16
−
ns
t_CLP
minimum time for active clamp note 7; see Fig.9
3
−
−
µs
Notes
1. Low frequency ramp signal (V_I(p-p) = full-scale and 64 µs period) combined with a sinewave input voltage
(V_I(p-p) = 0.25 full-scale, f_i = maximum permitted frequency) at the input.
2. The input conditions are related as follows:
a) Y channel: V_I(p-p) = 1.0 V; f_i = 4.43 MHz
b) U/V channel: V_I(p-p) = 1.0 V; f_i = 1.5 MHz.
3. Supply voltage ripple rejection:
a) SVRR1 is the variation of the input voltage producing output code 127 (code 15) for supply voltage variation
of 0.5 V:
SVRR1 = 20 log -^∆--_∆--V--V--^I--_C⁽--¹-_C--²--_A7---⁾-
b) SVRR2 is the relative variation of the full-scale range of analog input for a supply voltage variation of 0.5 V:
SVVR2 = -^∆-----⁽_V--V--I--^I₍--₀-⁽--⁰₎--⁾--_–--^–--V--V--_I---^I₍--₂⁽--²⁵--⁵-₅--⁵₎---⁾--⁾-- × _∆-----V---1-_C---_C----_A-
4. Full-scale sinewave (f_i = 4.43 MHz for Y and f_i = 1.5 MHz for U and V; f_clk = 20 MHz).
5. The number of effective bits is measured using a 20 MHz clock frequency. This value is given for a 4.43 MHz input
frequency on the Y channel (1.5 MHz on the U and V channels). This value is obtained via a Fast Fourier Transform
(FFT) treatment taking 4 × T_clk (clock periods) acquisition points per period. The calculation takes into account all
harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
6. Output data acquisition is available after the maximum delay time of t_d.
7. U and V output data is not valid during t_CLP.
1995 Mar 09
8