TDA8755 Datasheet, PDF (4/20 Pages) NXP Semiconductors – YUV 8-bit video low-power analog-to-digital interface

Philips Semiconductors
YUV 8-bit video low-power
analog-to-digital interface
Product specification
TDA8755
PINNING
SYMBOL
n.c.
REG1
INY
REG2
CLPY
V_CCA
INU
SDN
INV
AGND
CLPU
CLPV
REG3
CE
CLP
HREF
CLK
DGND
D'0
D'1
D'2
D'3
V_CCO
D0
D1
D2
D3
D4
D5
D6
D7
V_CCD
PIN
DESCRIPTION
1 not connected
2 decoupling input (internal
stabilization loop decoupling)
3 Y analog voltage input
4 decoupling input (internal
stabilization loop decoupling)
5 Y clamp capacitor connection
6 analog positive supply voltage
(+5 V)
7 U analog voltage input
8 stabilizer decoupling node and
analog reference voltage (+3.35 V)
9 V analog voltage input
10 analog ground
11 U clamp capacitor connection
12 V clamp capacitor connection
13 decoupling input (internal
stabilization loop decoupling)
14 chip enable input (TTL level input
active LOW)
15 clamp control input
16 horizontal reference signal
17 clock input
18 digital ground
19 V data output; bit 0 (n−1)
20 V data output; bit 1 (n)
21 U data output; bit 0 (n−1)
22 U data output; bit 1 (n)
23 positive supply voltage for output
stages (+5 V)
24 Y data output; bit 0 (LSB)
25 Y data output; bit 1
26 Y data output; bit 2
27 Y data output; bit 3
28 Y data output; bit 4
29 Y data output; bit 5
30 Y data output; bit 6
31 Y data output; bit 7 (MSB)
32 digital positive supply voltage (+5 V)
handbook, halfpage
n.c. ¹
32 ^VCCD
REG1 2
31 D7
INY 3
30 D6
REG2 4
29 D5
CLPY 5
VCCA ₆
28 D4
27 D3
INU 7
26 D2
SDN 8
INV 9
AGND 10
TDA8755
25 D1
24 D0
23 ^VCCO
CLPU 11
22 D'3
CLPV 12
21 D'2
REG3 13
20 D'1
CE 14
19 D'0
CLP 15
18 DGND
HREF 16
17 CLK
MLA728 - 1
Fig.2 Pin configuration.
1995 Mar 09
4