TDA8706A Datasheet, PDF (8/20 Pages) NXP Semiconductors – 6-bit analog-to-digital converter with multiplexer and clamp

Philips Semiconductors
6-bit analog-to-digital converter
with multiplexer and clamp
Product specification
TDA8706A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Timing (f_clk = 40 MHz; C_L = 20 pF); T_amb = 25 °C; see Fig.3
OUTPUT DATA; note 3
t_ds
sampling delay time
t_h
output hold time
t_d
output delay time
V_DDO = 4.75 V
V_DDO = 3.15 V
V_DDO = 2.70 V
−
−
7
ns
5
−
−
ns
−
12
15
ns
−
17
20
ns
−
18
21
ns
SELECT INPUT SIGNALS SR, SG, SB AND CLP
t_su
set-up time SR, SG and SB with no overlap; see Fig.3 10
−
−
ns
with overlap
see Fig.4
ns
t_r
rise time SR, SG and SB 10% to 90%
t_f
fall time SR, SG and SB
90% to 10%
t_over
R, G and B (active) overlap see Fig.4
time with respect to select
signals SR, SG and SB
4
6
4
6
0
−
−
ns
−
ns
−
ns
t_CLPP
t_MH
clamp pulse time
multiplexer hold time
SR, SG and SB
C_CLP = 10 nF
−
3
9
−
−
µs
−
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
2. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
3. Output data acquisition: the output data is available after the maximum delay time of t_d.
1996 Jul 30
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