TDA8706A Datasheet, PDF (7/20 Pages) NXP Semiconductors – 6-bit analog-to-digital converter with multiplexer and clamp

Philips Semiconductors
6-bit analog-to-digital converter
with multiplexer and clamp
Product specification
TDA8706A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
ANALOG INPUTS RED, GREEN AND BLUE; see Table 1
V_i(p-p)
I_i
C_clamp
input voltage amplitude
(peak-to-peak value)
input current
clamp coupling capacitance
V_DDA = V_DDD = 3 V;
T_amb = 25 °C
V_DDA = V_DDD = 5 V;
T_amb = 25 °C
Reference voltages for the resistor ladder; see Table 1
V_RB
∆T_VRB
reference voltage BOTTOM
temperature variation on
V_RB
V_DDA = 3 V
V_DDA = 5 V
T_amb = 0 to 50 °C
Outputs
0.665
0.625
−
1
−
−
−
0.70
0.735
0.66
0.695
−
10
10
1 00
V_DDA − 1.19 −
V_DDA − 1.13 −
0.7
−
DIGITAL OUTPUTS D5 TO D0 (REFERENCED TO V_SSD)
V_OL
LOW level output voltage I_O = 1 mA
V_OH
HIGH level output voltage I_O = −1 mA
Switching characteristics
0
−
V_DDO − 0.5 −
0.5
V_DDO
CLOCK INPUT CLK; see Fig.3; note 1
f_clk(max)
f_mux(max)
maximum clock frequency
maximum multiplexer
frequency
40
−
−
20
−
−
t_CPH
clock pulse width HIGH
8
−
−
t_CPL
clock pulse width LOW
8
−
−
t_r
clock rise time
10% to 90%; f_clk ≤ 25 MHz; −
−
10
LOW = V_SSD, HIGH = V_DDD
t_f
clock fall time
90% to 10%; f_clk ≤ 25 MHz; −
−
10
LOW = V_SSD, HIGH = V_DDD
Analog signal processing
LINEARITY
INL
integral non-linearity
DNL
differential non-linearity
EFFECTIVE BITS; note 2
EB
effective bits
f_clk = 40 MHz; ramp input; −
T_amb = 25 °C
f_clk = 40 MHz; ramp input; −
T_amb = 25 °C
f_clk = 40 MHz; f_i = 4.43 MHz −
±0.25
±0.6
±0.20
±0.5
5.8
−
UNIT
V
V
µA
nF
V
V
mV/°C
V
V
MHz
MHz
ns
ns
ns
ns
LSB
LSB
bits
1996 Jul 30
7