SA56600-42 Datasheet, PDF (8/12 Pages) NXP Semiconductors – System reset for lithium battery backup

Philips Semiconductors
System reset for lithium battery back-up
Product data
SA56600-42
Timing diagram
The Timing Diagram shown in Figure 15 depicts the operation of the
SA56600-42 in its intended application, with a 3.0 V Lithium battery
serving as a backup power source for external SRAM circuitry (see
the Simplified system diagram, Figure 1). Letters indicate events
along the Time axis.
A: At ‘A’, the V_CC primary power source is off. As a result of the
backup battery, the CS and V_OUT outputs are almost up to the
Lithium battery potential (V_B). All other outputs (Y, RESET, and CS)
are at or very near ground potential.
B - C: At ‘B’, the V_CC voltage begins to rise. Also the RESET
voltage initially rises but then abruptly returns to a LOW state at ‘C’.
when the V_CC voltage reaches the level which activates the internal
bias circuitry and asserts RESET to a logic LOW. This occurs at
approximately 0.8 volts.
D - E: At ‘D’ the internal 3.3 V detection circuit is activated when
V_CC voltage rises to 3.3 V. The circuit causes the PNP series pass
switching transistor in the output to activate, connecting the main
power supply voltage (V_CC) to the output. This causes the Lithium
battery to be automatically disconnected from V_OUT by back-biasing
the Schottky diode. As a result, CS and V_OUT begin to rise with V_CC.
E: At ‘E’, V_CC has risen to the upper detection threshold (V_S plus
hysteresis) as sensed by the device’s internal 4.2 V detection circuit.
This event signals that the output voltage is adequate to support full
operation of the associated external computer circuitry. RESET goes
HIGH, allowing the microprocessor circuitry to operate.
Simultaneously, CS also goes HIGH, signaling the SRAM to start
receiving data. CS goes LOW as a result of Y simultaneously being
at a LOW state.
Y controls the CS output. As long as Y is LOW, the CS output is
enabled.
F: As V_CC continues to rise, RESET, CS, and V_OUT also continue to
rise. Just before ‘F’, Y is asserted HIGH by the microprocessing
circuitry. This causes CS to change from a LOW state to a HIGH
state. Following ‘F’ the microprocessing circuitry is signaling Y
through repetitive cycles. This causes CS to also cycle, but has no
effect on the battery circuit.
G: At ‘G’, the V_CC voltage begins to fall. As a result RESET, CS,
and V_CC fall.
H: When the V_CC voltage falls to V_S (4.2 V) it is detected by the
internal 4.2 V detector circuit. The detector circuit forces RESET and
CS LOW, deselecting the SRAM and stopping data storage and
retrieval. The PNP series pass switching transistor disconnects the
primary input source voltage from the output, transferring the SRAM
to the backup battery. In addition, because Y is already at a LOW
state, CS rises abruptly close to V_S followed by a continued fall to
V_B (Lithium battery potential), following V_CC.
J: At ‘J’, V_OUT has also fallen with V_CC to a level that is now
dictated by the Lithium battery potential. The Lithium battery is now
maintaining the V_OUT voltage to preserve the SRAM data.
K - L: As the V_CC voltage falls to a level which no longer allows the
internal bias circuitry to remain active, the assertion of RESET can
no longer be maintained. RESET rises slightly, then falls to ground
as V_CC falls to ground.
M: Y is asserted HIGH again by the microprocessor, but because
V_CC is below V_S, CS remains HIGH and CS remains LOW,
preventing the SRAM from being selected.
V_CC
0
5.0
V_S
V_B
V_OPL
Y
0
RESET
0
V_RSL
CS
≤V_B
0
V_RSH
V_CSL
V_CSH
CS
0
V_CSL
V_OUT
0
A
V_{O3, O4}
V_CSH
V_{O1, O2}
BC
D EF
TIME
Figure 15. Timing diagram.
2001 Jun 19
8
GH J
KL
SL01341