SA56600-42 Datasheet, PDF (7/12 Pages) NXP Semiconductors – System reset for lithium battery backup

Philips Semiconductors
System reset for lithium battery back-up
Product data
SA56600-42
TECHNICAL DESCRIPTION
The SA56600-42 provides battery back-up functions to protect
SRAM data in computer memory systems. In addition, it provides
RESET, Chip Select HIGH (CS), and Chip Select LOW (CS)
outputs. The device incorporates a 3.3 V detection circuit,
4.2 V detection circuit, PNP switching transistor, and Schottky diode
for low drop lithium battery connection to the output.
During power-up, RESET is actively asserted (LOW logic state) at
V_CC voltages as low as 0.8 V and does not output a release (HIGH
logic state) until V_CC attains 4.2 V plus hysteresis. CS, in a similar
manner, only transitions to a HIGH logic state when V_CC attains
4.2 V plus hysteresis. This ensures adequate voltage being present
at the output of the SA56600 for proper operation of the associated
computer system.
If the V_CC voltage falls below 4.2 V, CS and RESET both go to a
LOW logic state. During this time, with CS in a LOW logic state, no
data ca be read from, or written to, the SRAM device. If the primary
voltage (V_CC) continues to fall to 3.3 V and below, the PNP
switching transistor disconnects the primary input source power
(V_CC) from the output and the Schottky diode automatically couples
the lithium battery power to the output of the SA56600 to supply
sustaining power to the SRAM memory.
The SA56600 provides complementary CS and CS outputs. The
outputs differ in ways other than being simple complements of each
other. The logic state of CS is strictly a function of V_CC voltage.
When V_CC is above 4.2 V plus hysteresis, CS is in a HIGH logic
state. When V_CC is below 4.2 V, CS is in a LOW logic state.
CS goes to a LOW logic state only when V_CC is above 4.2 V plus
hysteresis, and Y is simultaneously at a LOW logic state. If Y is not
a LOW logic state (is open or at a HIGH logic state) CS will be at a
HIGH logic state. Essentially, Y functions as a control switch for CS
and is normally used as an input gating signal from the computer’s
microprocessor.
Caution should be exercised in the application to keep the voltage
on Y to less than 5.0 V when the V_CC voltage is less than 4.2 V to
avoid breaking down the Emitter-Base junction of the internal NPN
transistor associated with Y. Breakdown of the junction may produce
excessive current flow causing damage to the device. When the
V_CC voltage is less than 4.2 V, the base of the NPN transistor
associated with the Y is at a LOW logic state and most susceptible
to an overvoltage on Y.
Recovering primary V_CC power is sensed by the 3.3 V detection
circuit. The PNP switching transistor is activated when the applied
V_CC voltage reaches 3.3 V plus hysteresis. When this event occurs,
the Schottky diode becomes back-biased, automatically
disconnecting the lithium battery from the output and the SRAM is
once again supported by the primary V_CC power source. Full
operation is restored when the applied primary V_CC voltage reaches
the required 4.2 V plus hysteresis value. This level is sensed by the
4.2 V detection circuit. RESET and CS are then caused to go to a
HIGH logic state, and the computer memory is back in full operation
without any loss of SRAM data.
V_CC
C1
GND
SA56600–42
8
RR
R
47 kΩ
R
R
R
R
R
1
R
47 kΩ
75 3
Y CS CS
R
R
R
R
6 ^VOUT
4 ^VBATT
PNP
SWITCHING
TRANSISTOR
VOLTAGE
TO SRAM
R1
C2
R
R
R
R
RR
LITHIUM
BATTERY
1
GND
2
RESET
R1 = OVERVOLTAGE CURRENT LIMITING RESISTOR
C1, C2 = POWER SUPPLY BYPASS CAPACITOR
SL01342
Figure 14. Functional diagram.
2001 Jun 19
7