74HC195 Datasheet, PDF (8/9 Pages) NXP Semiconductors – 4-bit parallel access shift register

Philips Semiconductors
4-bit parallel access shift register
AC WAVEFORMS
Product specification
74HC/HCT195
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3V; V_I = GND to 3 V.
Fig.6
Waveforms showing the clock (CP) to
output (Q_n) propagation delays, the clock
pulse width, the output transition times and
the maximum clock frequency.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3V; V_I = GND to 3 V.
Fig.7
Waveforms showing the master reset
(MR) pulse width, the master reset to output
(Q_n) propagation delays and the master
reset to clock (CP) removal time
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3V; V_I = GND to 3 V.
Fig.8 Waveforms showing the data set-up
and hold times for J, K and D_n inputs.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3V; V_I = GND to 3 V.
Fig.9 Waveforms showing the set-up and hold
times from the parallel enable input
(PE) to the clock (CP).
December 1990
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