74HC195 Datasheet, PDF (2/9 Pages) NXP Semiconductors – 4-bit parallel access shift register

Philips Semiconductors
4-bit parallel access shift register
Product specification
74HC/HCT195
FEATURES
• Asynchronous master reset
• J, K, (D) inputs to the first stage
• Fully synchronous serial or parallel data transfer
• Shift right and parallel load capability
• Complement output from the last stage
• Output capability: standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT195 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT195 performs serial, parallel,
serial-to-parallel or parallel-to-serial data transfer at very
high speeds. The “195” operates on two primary modes:
shift right (Q_o→Q₁) and parallel load, which are controlled
by the state of the parallel load enable (PE) input. Serial
data enters the first flip-flop (Q₀) via the J and K inputs
when the PE input is HIGH and shifted one bit in the
direction Q₀ → Q₁ → Q₂ → Q₃ following each
LOW-to-HIGH clock transition. The J and K inputs provide
the flexibility of the JK type input for special applications
and by tying the pins together, the simple D-type input for
general applications. The “195” appears as four common
clocked D flip-flops when the PE input is LOW.
After the LOW-to-HIGH clock transition, data on the
parallel inputs (D₀ to D₃) is transferred to the respective
Q₀ to Q₃ outputs. Shift left operation (Q₃ → Q₂) can be
achieved by tying the Q_n outputs to the D_n-1 inputs and
holding the PE input LOW.
All parallel and serial data transfers are synchronous,
occurring after each LOW-to-HIGH clock transition.
There is no restriction on the activity of the J, K, D_n and
PE inputs for logic operation other than the set-up and
hold time requirements. A LOW on the asynchronous
master reset (MR) input sets all Q outputs LOW,
independent of any other input condition.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
CONDITIONS
t_PHL/ t_PLH
f_max
C_I
C_PD
propagation delay CP to Q_n
maximum clock frequency
input capacitance
power dissipation capacitance per package
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1,5 V
TYPICAL
HC
15
57
3.5
105
HCT
15
57
3.5
105
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2