74HC03 Datasheet, PDF (8/8 Pages) NXP Semiconductors – Quad 2-input NAND gate

Philips Semiconductors
Quad 2-input NAND gate
APPLICATION INFORMATION
Product specification
74HC/HCT03
(1) R_ON(max) = 0.26 V / 4 mA = 65 Ω (at 25 °C)
(a)
(b)
Fig.9 Pull-up configuration.
(1) V_CC (R) = 2.0 V; V_IL = 0.5 V.
(2) V_CC (R) = 5.0 V; V_IL = 0.8 V.
(3) V_CC (R) = 4.5 V; V_IL = 1.35 V.
(4) V_CC (R) = 6.0 V; V_IL = 1.8 V.
Fig.10 Minimum resistive load as a function of the pull-up voltage.
Notes to Figs 9 and 10
If V_P − V_CC (R) > 0.5 V a positive current will flow into the receiver (as described in the “USER GUIDE”; input/output
protection), this will not affect the receiver provided the current does not exceed 20 mA. At V_CC < 4.5 V, R_{ON (max)} is not
guaranteed; R_ON(max) can be estimated using Figs 33 and 34 in the “USER GUIDE”.
Note to Application information
All values given are typical unless otherwise specified.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
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