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74HC03 Datasheet, PDF (2/8 Pages) NXP Semiconductors – Quad 2-input NAND gate | |||
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Philips Semiconductors
Quad 2-input NAND gate
Product speciï¬cation
74HC/HCT03
FEATURES
⢠Level shift capability
⢠Output capability: standard (open drain)
⢠ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT03 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT03 provide the 2-input NAND function.
The 74HC/HCT03 have open-drain N-transistor outputs,
which are not clamped by a diode connected to VCC. In
the OFF-state, i.e. when one input is LOW, the output
may be pulled to any voltage between GND and VOmax.
This allows the device to be used as a LOW-to-HIGH or
HIGH-to-LOW level shifter. For digital operation and
OR-tied output applications, these devices must have a
pull-up resistor to establish a logic HIGH level.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
tPZL/ tPLZ
CI
CPD
PARAMETER
propagation delay
input capacitance
power dissipation capacitance per gate
CONDITIONS
TYPICAL
HC HCT
CL = 15 pF; RL = 1 kâ¦; VCC = 5 V 8
10
3.5
3.5
notes 1, 2 and 3
4.0
4.0
UNIT
ns
pF
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD Ã VCC2Ã fi + â (CL Ã VCC2 Ã fo) + â (VO2/RL) Ã duty factor LOW, where:
fi = input frequency in MHz
fo = output frequency in MHz
VO = output voltage in V
CL = output load capacitance in pF
VCC = supply voltage in V
RL = pull-up resistor in Mâ¦
â (CL Ã VCC2 Ã fo) = sum of outputs
â (VO2/RL) = sum of outputs
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC â 1.5 V
3. The given value of CPD is obtained with:
CL = 0 pF and RL = â
ORDERING INFORMATION
See â74HC/HCT/HCU/HCMOS Logic Package Informationâ.
December 1990
2
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