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| 74F50109 Datasheet, PDF (8/12 Pages) NXP Semiconductors – Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics | |||
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Philips Semiconductors
Synchronizing dual JâK positive edge-triggered
flip-flop with metastable immune characteristics
Product specification
74F50109
AC WAVEFORMS
Jn, Kn
CPn
Qn
Qn
VM
VM
tsu(L) th(L)
1/fmax
VM
VM
tw(H)
tPLH
VM
tsu(H)
tw(L)
VM
th(H)
VM
tPHL
VM
tPHL
VM
tPLH
VM
VM
SF00139
Waveform 1. Propagation delay for data to output, data
setup time and hold times, and clock
width, and maximum clock frequency
SDn or RDn
CPn
VM
trec
VM
SF00603
Waveform 3. Recovery time for set or reset to output
NOTES:
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
TEST CIRCUIT AND WAVEFORM
tw(L)
SDn VM
VM
RDn
tPLH
tw(L)
VM
VM
tPHL
Qn
VM
tPHL
VM
tPLH
Qn
VM
VM
SF00050
Waveform 2. Propagation delay for set and reset to output,
set and reset pulse width
Qn, Qn
Qn, Qn
VM
tsk(o)
Waveform 4. Output skew
VM
SF00590
VIN
PULSE
GENERATOR
VCC
VOUT
D.U.T.
NEGATIVE
PULSE
90%
tw
VM
10%
tTHL (tf )
VM
10%
tTLH (tr )
90%
AMP (V)
0V
RT
CL RL
Test Circuit for Totem-Pole Outputs
POSITIVE
PULSE
10%
tTLH (tr )
90%
VM
tw
tTHL (tf )
90%
VM
AMP (V)
10%
0V
DEFINITIONS:
RL = Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
Input Pulse Definition
family
74F
INPUT PULSE REQUIREMENTS
amplitude VM rep. rate
tw
tTLH
3.0V 1.5V 1MHz 500ns 2.5ns
tTHL
2.5ns
SF00006
September 14, 1990
8
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