74F50109 Datasheet, PDF (7/12 Pages) NXP Semiconductors – Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics

Philips Semiconductors
Synchronizing dual J–K positive edge-triggered
flip-flop with metastable immune characteristics
Product specification
74F50109
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
LIMITS
T_amb = +25°C
V_CC = +5.0V
C_L = 50pF,
R_L = 500Ω
T_amb = 0°C to +70°C
V_CC = +5.0V ± 10%
C_L = 50pF,
R_L = 500Ω
MIN TYP MAX
MIN
MAX
f_max
Maximum clock frequency
Waveform 1
130 150
90
t_PLH
Propagation delay
t_PHL
CPn to Qn or Qn
Waveform 1
2.0
3.8
6.0
2.0
3.8
6.0
2.0
2.0
6.5
6.5
t_PLH
Propagation delay
t_PHL
SDn, RDn to Qn or Qn
Waveform 2
3.5
5.5
8.0
3.5
5.5
8.0
3.0
3.0
8.5
8.5
t_sk(o)
Output skew^{1, 2}
Waveform 4
1.5
1.5
NOTES:
1. | t_PN actual – t_PM actual| for any output compared to any other output where N and M are either LH or HL.
2. Skew times are valid only under same test conditions (temperature, V_CC, loading, etc.,).
UNIT
ns
ns
ns
ns
AC SETUP REQUIREMENTS
SYMBOL
PARAMETER
t_su (H)
t_su(L)
t_h (H)
t_h (L)
t_w (H)
t_w (L)
t_w (L)
t_rec
Setup time, high or low
Jn, Kn to CPn
Hold time, high or low
Jn, Kn to CPn
CPn pulse width,
high or low
SDn or RDn pulse width, low
Recovery time
SDn or RDn to CP
TEST
CONDITION
Waveform 1
Waveform 1
Waveform 1
Waveform 2
Waveform 3
LIMITS
T_amb = +25°C
V_CC = +5.0V
C_L = 50pF,
R_L = 500Ω
T_amb = 0°C to +70°C
V_CC = +5.0V ± 10%
C_L = 50pF,
R_L = 500Ω
MIN TYP MAX
MIN
MAX
1.5
2.0
1.5
2.0
1.0
1.5
1.0
1.5
3.0
3.5
4.0
5.0
3.5
4.0
3.0
3.5
UNIT
ns
ns
ns
ns
ns
September 14, 1990
7