74F50109 Datasheet, PDF (5/12 Pages) NXP Semiconductors – Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics

Philips Semiconductors
Synchronizing dual J–K positive edge-triggered
flip-flop with metastable immune characteristics
Product specification
74F50109
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’
10⁶ 10⁸
10¹⁰ 10¹²
10¹²
10¹¹
10,000 years
10¹⁰
MTBF in seconds
100 years ₁₀₉
10⁸
one year
10⁷
10¹⁴
10¹⁵ = f_Cf_I
10⁶
one week
7
8
9
10
t’ in nanoseconds
NOTE: V_CC = 5V, T_amb = 25°C, τ =135ps, To = 9.8 X 10⁸ sec
Figure 4.
SF00589
TYPICAL VALUES FOR τ AND T₀ AT VARIOUS V_CCS AND TEMPERATURES
T_amb = 0°C
T_amb = 25°C
V_CC
5.5V
τ
125ps
T₀
1.0 X 10⁹ sec
τ
138ps
T₀
5.4 X 10⁶ sec
5.0V
115ps
1.3 X 10¹⁰ sec
135ps
9.8 X 10⁶ sec
4.5V
115ps
3.4 X 10¹³ sec
132ps
5.1 X 10⁸ sec
τ
160ps
167ps
175ps
T_amb = 70°C
T₀
1.7 X 10⁵ sec
3.9 X 10⁴ sec
7.3 X 10⁴ sec
FUNCTION TABLE
INPUTS
SD RD CP J K
LHXXX
HLXXX
L LXXX
HH ↑ X X
HH↑ h l
HH↑ h h
HH ↑
l
l
HH↑ l h
OUTPUTS
QQ
HL
LH
HH
qq
qq
HL
LH
qq
OPERATING
MODE
Asynchronous set
Asynchronous reset
Undetermined*
Hold
Toggle
Load ”1” (set)
Load ”0” (reset)
Hold ’no change”
NOTES:
H = High–voltage level
h = High–voltage level one setup time prior to
low–to–high clock transition
L = Low–voltage level
l = Low–voltage level one setup time prior to
low–to–high clock
transition
q = Lower case indicate the state of the referenced
output prior to the low–to–high clock transition
X = Don’t care
↑ = Low–to–high clock transition
↑ = Not low–to–high clock transition
* = Both outputs will be high if both SD and RD go low
simultaneously
September 14, 1990
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