SAA7109A Datasheet, PDF (79/197 Pages) NXP Semiconductors – HD-CODEC

Philips Semiconductors
HD-CODEC
Product specification
SAA7108AE; SAA7109AE
10 INPUT/OUTPUT INTERFACES AND PORTS OF
DIGITAL VIDEO DECODER PART
The SAA7108AE; SAA7109AE has 5 different I/O
interfaces. These are:
• Analog video input interface, for analog CVBS and/or
Y and C input signals
• Audio clock port
• Digital real-time signal port (RT port)
• Digital video expansion port (X port), for unscaled digital
video input and output
• Digital image port (I port) for scaled video data output
and programming
• Digital host port (H port) for extension of the image port
or expansion port from 8 to 16-bit.
10.1 Analog terminals
The SAA7108AE; SAA7109AE has 6 analog inputs
AI21 to AI24, AI11 and AI12 (see Table 38) for composite
video CVBS or S-video Y/C signal pairs. Additionally, there
are two differential reference inputs, which must be
connected to ground via a capacitor equivalent to the
decoupling capacitors at the 6 inputs. There are no
peripheral components required other than the decoupling
capacitors and 18 Ω/56 Ω termination resistors, one set
per connected input signal (see also application example
in Fig.53). Two anti-alias filters are integrated, and self
adjusting via the clock frequency.
Clamp and gain control for the two ADCs are also
integrated. An analog video output pin (AOUT) is provided
for testing purposes.
Table 38 Analog pin description
SYMBOL
PIN
I/O
AI24 to AI21 P6, P7, P9 I
and P10
AI12 and AI11 P11 and P13
AOUT
M10
O
AI1D and AI2D P12 and P8 I
DESCRIPTION
analog video signal inputs, e.g. 2 CVBS signals and
two Y/C pairs can be connected simultaneously
analog video output, for test purposes
analog reference pins for differential ADC operation
BIT
MODE3 to MODE0
AOSL1 and AOSL0
−
10.2 Audio clock signals
The SAA7108AE; SAA7109AE also synchronizes the audio clock and sampling rate to the video frame rate, via a very
slow PLL. This ensures that the multimedia capture and compression processes always gather the same predefined
number of samples per video frame.
An audio master clock AMCLK and two divided clocks, ASCLK and ALRCLK, are generated; see Table 39.
• ASCLK: can be used as audio serial clock
• ALRCLK: audio left/right channel clock.
The ratios are programmable; see Section 9.6.
Table 39 Audio clock pin description
SYMBOL PIN I/O
DESCRIPTION
BIT
AMCLK K12 O
AMXCLK J12 I
audio master clock output
external audio master clock input for the clock
division circuit, can be directly connected to
output AMCLK for standard applications
ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0]
and ACNI[21:0] 36H[5:0] 35H[7:0]
34H[7:0]
−
ASCLK
K14 O
serial audio clock output, can be synchronized to SDIV[5:0] 38H[5:0] and SCPH[3AH[0]]
rising or falling edge of AMXCLK
ALRCLK J13 O
audio channel (left/right) clock output, can be LRDIV[5:0] 39H[5:0] and LRPH[3AH[1]]
synchronized to rising or falling edge of ASCLK
2004 Jun 29
79