SAA7109A Datasheet, PDF (4/197 Pages) NXP Semiconductors – HD-CODEC

Philips Semiconductors
HD-CODEC
Product specification
SAA7108AE; SAA7109AE
1.3 Video encoder
• Digital PAL/NTSC encoder with integrated high quality
scaler and anti-flicker filter for TV output from a PC
• Supports Intel® Digital Video Out (DVO) low voltage
interfacing to graphics controller
• 27 MHz crystal-stable subcarrier generation
• Maximum graphics pixel clock 85 MHz at double edged
clocking, synthesized on-chip or from external source
• Programmable assignment of clock edge to bytes (in
double edged mode)
• Synthesizable pixel clock (PIXCLK) with minimized
output jitter, can be used as reference clock for the VGC,
as well
• PIXCLK output and bi-phase PIXCLK input (VGC clock
loop-through possible)
• Hot-plug detection through dedicated interrupt pin
• Supported VGA resolutions for PAL or NTSC legacy
video output up to 1280 × 1024 graphics data at
60 or 50 Hz frame rate
• Supported VGA resolutions for HDTV output up to
1920 × 1080 interlaced graphics data at 60 or 50 Hz
frame rate
• Three Digital-to-Analog Converters (DACs) for CVBS
(BLUE, C_B), VBS (GREEN, CVBS) and C (RED, C_R) at
27 MHz sample rate (signals in parenthesis are
optionally selected), all at 10-bit resolution
• Non-interlaced C_B-Y-C_R or RGB input at maximum
4 : 4 : 4 sampling
• Downscaling and upscaling from 50 to 400 %
• Optional interlaced C_B-Y-C_R input of Digital Versatile
Disk (DVD) signals
• Optional non-interlaced RGB output to drive second
VGA monitor (bypass mode, maximum 85 MHz)
• 3 × 256 bytes RGB Look-Up Table (LUT)
• Support for hardware cursor
• HDTV up to 1920 × 1080 interlaced and 1280 × 720
progressive, including 3-level sync pulses
• Programmable border colour of underscan area
• Programmable 5 line anti-flicker filter
• On-chip 27 MHz crystal oscillator (3rd-harmonic or
fundamental 27 MHz crystal)
• Fast I²C-bus control port (400 kHz)
• Encoder can be master or slave
• Adjustable output levels for the DACs
• Programmable horizontal and vertical input
synchronization phase
• Programmable horizontal sync output phase
• Internal Colour Bar Generator (CBG)
• Optional support of various Vertical Blanking Interval
(VBI) data insertion
• Macrovision Pay-per-View copy protection system
rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option;
this applies to SAA7108AE only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited. Please
contact your nearest Philips Semiconductors sales
office for more information.
1.4 Common features
• 5 V tolerant digital I/O ports
• I²C-bus controlled (full read-back ability by an external
controller, bit rate up to 400 kbits/s)
• Versatile power-save modes
• Boundary scan test circuit complies with the “IEEE Std.
1149.b1-1994” (separate ID codes for decoder and
encoder)
• Monolithic CMOS 3.3 V device
• BGA156 package
• Moisture Sensitive Level (MSL): e3.
2 APPLICATIONS
• Notebook (low-power consumption)
• PCMCIA card application
• AGP based graphics cards
• PC editing
• Image processing
• Video phone applications
• INTERCAST and PC teletext applications
• Security applications
• Hybrid satellite set-top boxes.
2004 Jun 29
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